30. ISMVL 2000: Portland, Oregon, USA

• Message from the Symposium Chair.
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• Message from the Co-Chairs.
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• Reviewers.
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Session 1: Invited Address

• Dan W. Hammerstrom:
  Computational Neurobiology Meets Semiconductor Engineering. 3-
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Session 2a: Neural and Threshold Nets

• Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka:
  Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. 15-20
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• Masayuki Matsumoto, Yoshinori Ueda, Isami Nomoto:
  The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models. 21-26
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• Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka:
  Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. 27-32
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• Alioune Ngom, Ivan Stojmenovic, Ratko Tosic:
  The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons. 33-
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Session 2b: Spectral Methods

• Rolf Drechsler, Mitchell A. Thornton, David Wessels:
  MDD-Based Synthesis of Multi-Valued Logic Networks. 41-46
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• Bogdan J. Falkowski, Susanto Rahardja:
  Fast Transforms for Multiple-Valued Input Binary Output PLI Logic. 47-52
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• Rolf Drechsler, Mitchell A. Thornton:
  Computation of Spectral Information from Logic Netlists. 53-58
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• Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim:
  Fault Analysis of the Multiple Valued Logic Using Spectral Method. 59-
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Session 3: Invited Address

• Jacek M. Zurada:
  Neural Networks: Binary Monotonic and Multiple-Valued. 67-
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Session 4a: Decomposition and Data Mining

• Szymon Jaroszewicz, Dan A. Simovici:
  Data Mining of Weak Functional Decompositions. 77-82
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• Artur Chojnacki, Lech Józwiak:
  Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. 83-90
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• Tsutomu Sasao:
  On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions. 91-
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Session 4b: Algebra I

• Noboru Takagi, Kyoichi Nakashima:
  Some Properties of Discrete Interval Truth Valued Logic. 101-106
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• Tomoko Ninomiya, Masao Mukaidono:
  Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic. 107-112
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• Agata Ciabattoni:
  On Urquhart's C Logic. 113-
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Session 5a: Fuzzy Logic

• Martine De Cock, Etienne E. Kerre:
  A New Class of Fuzzy Modifiers. 121-126
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• Karsten Strehl, Claudio Moraga, Karl-Heinz Temme, Radomir S. Stankovic:
  Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases. 127-132
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• Helmut Thiele:
  On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach. 133-
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Session 5b: Reed-Muller Logic and Its Extensions

• Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko:
  Experiments on FPRM Expressions for Partially Symmetric Logic Functions. 141-146
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• Hafiz Md. Hasan Babu, Tsutomu Sasao:
  Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. 147-152
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• Susanto Rahardja, Bogdan J. Falkowski:
  A New Algorithm to Compute Quaternary Reed-Muller Expansions. 153-
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Session 6: Invited Address

• Adrian Stoica:
  Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems. 161-
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Session 7a: Logic and Algebra

• Janusz A. Brzozowski:
  De Morgan Bisemilattices. 173-178
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• Stefano Aguzzoli, Brunella Gerla:
  Finite-Valued Approximations of Product Logic. 179-184
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• Yann Loyer, Nicolas Spyratos, Daniel Stamate:
  Integration of Information in Four-Valued Logics under Non-Uniform Assumptions. 185-
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Session 7b: Decision Diagrams

• Dragan Jankovic, Wolfgang Günther, Rolf Drechsler:
  Lower Bound Sifting for MDDs. 193-198
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• Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
  Implementation of Multiple-Output Functions Using PQMDDs. 199-205
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• Radomir S. Stankovic, Milena Stankovic, Jaakko Astola, Karen Egiazarian:
  Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams. 206-
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Session 8a: Circuits I

• Mostafa H. Abd-El-Barr, Abdullah Al-Mutawa:
  Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits. 215-220
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• Hyeon Kyeong Seong, Jai Seok Choi, Boo Sik Shin, Heung-Soo Kim:
  Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS. 221-226
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• Xunwei Wu, Xuanchang Zhou:
  Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic. 227-
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Session 8b: Decision Diagrams and Test

• Harald Sack, Elena Dubrova, Christoph Meinel:
  Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions. 233-238
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• Frank Schmiedle, Wolfgang Günther, Rolf Drechsler:
  Dynamic Re-Encoding During MDD Minimization. 239-244
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• Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui:
  Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm. 245-
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Session 9a: Evolutionary and Information Theory Approaches

• Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, M. Opoka, Vlad P. Shmerko:
  Evolutionary Multi-Level Network Synthesis in Given Design Style. 253-258
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• Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato:
  An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. 259-264
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• Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic:
  Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). 265-
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Session 9b: Image and Language Processing

• Yutaka Hata, Syoji Kobashi, Naotake Kamiura, Yuri T. Kitamura, Toshio Yanagida:
  On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic. 273-278
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• Bogdan J. Falkowski, Lip-San Lim:
  Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra. 279-284
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• David Rine, Raiek Alnakari:
  A Four-Valued Logic B(4) of E(9) for Modeling Human Communication. 285-
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Session 10: Invited Address

• Ivo Düntsch, Wendy MacCaull, Ewa Orlowska:
  Structures with Many-Valued Information and Their Relational Proof Theory. 293-
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Session 11a: Circuits II

• Tetsuya Uemura, Toshio Baba:
  Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. 305-310
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• Gi-Noung Byun, Chol-U Lee, Seung-Yong Park, Heung-Soo Kim:
  A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation. 311-316
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• Takao Waho, Kazufumi Hattori, Kouji Honda:
  Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection. 317-322
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• Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
  Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. 323-
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Session 11b: Theorem-Proving and Applications

• Bernhard Beckert, Reiner Hähnle, Felip Manyà:
  The 2-SAT Problem of Regular Signed CNF Formulas. 331-336
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• Harald Ganzinger, Viorica Sofronie-Stokkermans:
  Chaining Techniques for Automated Theorem Proving in Many-Valued Logics. 337-344
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• Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi:
  High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. 345-
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Session 12: Invited Address

• Marwan A. Jabri, Ki-Young Park, Soo-Young Lee, Terrence J. Sejnowski:
  Properties of Independent Components of Self-Motion Optical Flow. 355-
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Session 13: Panel Discussion

Session 14: Invited Address

• M. Bauer, R. Alexis, Greg Atwood, B. Baltar, Al Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, Duane Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, K. Wojciechowski:
  A Multilevel-Cell 32MB Flash Memory. 367-
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Session 15a: Circuits III

• Dan Olson, K. Wayne Current:
  Hardware Implementation of ``Supplementary Symmetrical Logic Circuit Structure'' Concepts. 371-376
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• K. Wayne Current:
  Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. 377-381
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• Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
  Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. 382-
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Session 15b: Clones and Asynchronous Machines

• Masahiro Miyakawa, Ivo G. Rosenberg:
  Rigidity Problem of Autodual Clones. 391-395
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• Lucien Haddad, Hajime Machida, Ivo G. Rosenberg:
  On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones. 396-401
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• Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
  Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. 402-
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Session 16: Invited Address

• Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase:
  Silicon Single-Electron Devices and Their Applications. 411-
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Session 17a: Arithmetics and Systems

• Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
  DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. 423-429
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• Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
  An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. 430-437
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• Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama:
  Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. 438-
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Session 17b: Verification and Power Estimation

• Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
  A Method for Approximate Equivalence Checking. 447-452
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• Xunwei Wu, Massoud Pedram:
  Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic. 453-459
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• Elena Dubrova, Harald Sack:
  Probabilistic Verification of Multiple-Valued Functions. 460-466
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