13. CHARME 2005:
Saarbrücken,
Germany
Dominique Borrione, Wolfgang J. Paul (Eds.):
Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings.
Lecture Notes in Computer Science 3725 Springer 2005, ISBN 3-540-29105-9 BibTeX
Invited Talks
Tutorial
Functional Approaches to Design Description
Game Solving Approaches
Abstraction
Algorithms and Techniques for Speeding (DD-Based) Verification 1
Real Time and LTL Model Checking
Algorithms and Techniques for Speeding Verification 2
Evaluation of SAT-Based Tools
Model Reduction
Verification of Memory Hierarchy Mechanisms
Short Papers
- Ritwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan:
Symbolic Partial Order Reduction for Rule Based Transition Systems.
332-335
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- Christian Ferdinand, Reinhold Heckmann:
Verifying Timing Behavior by Abstract Interpretation of Executable Code.
336-339
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- Masahiro Fujita:
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.
340-344
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- Biniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu:
Deadlock Prevention in the Æthereal Protocol.
345-348
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- Daniel Große, Rolf Drechsler:
Acceleration of SAT-Based Iterative Property Checking.
349-353
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- Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle:
Error Detection Using BMC in a Parallel Environment.
354-358
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- Tsachy Kapschitz, Ran Ginosar:
Formal Verification of Synchronizers.
359-362
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- Panagiotis Manolios, Sudarshan K. Srinivasan:
A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.
363-366
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- João P. Marques Silva:
Improvements to the Implementation of Interpolant-Based Model Checking.
367-370
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- Petr Matousek, Ales Smrcka, Tomás Vojnar:
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design.
371-375
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- Katell Morin-Allory, David Cachera:
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.
376-379
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- Oliver Pell, Wayne Luk:
Resolving Quartz Overloading.
380-383
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- Mona Safar, M. Watheq El-Kharashi, Ashraf Salem:
FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.
384-387
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- Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Predictive Reachability Using a Sample-Based Approach.
388-392
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- ShengYu Shen, Ying Qin, Sikun Li:
Minimizing Counterexample of ACTL Property.
393-397
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- Alex Tsow, Steven D. Johnson:
Data Refinement for Synchronous System Specification and Construction.
398-401
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- William D. Young:
Introducing Abstractions via Rewriting.
402-405
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- Emmanuel Zarpas:
A Case Study: Formal Verification of Processor Critical Properties.
406-409
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Copyright © Sat May 16 23:01:13 2009
by Michael Ley (ley@uni-trier.de)
