ASP-DAC 1998:
Yokohama,
Japan
Proceedings of the ASP-DAC '98,
Asia and South Pacific Design Automation Conference 1998,
February 10-13,
1998 Pacifico Yokohama,
Yokohama,
Japan. IEEE,
IEEE Catalog Number 98EX121,
ISBN 0-7803-4425-1 (Softbound Edition),
ISBN 0-7803-4426-X (Microfiche Edition),
ISBN 0-7803-4427-8 (CD-ROM Edition),
Library of Congress:
97-80907,
CDROM produced by ACM SIGDA CD-ROM Project.
Session 1A:
High-Speed Design Techniques
- Kimikazu Sano, Koichi Narahara, Koichi Murata, Taiichi Otsuji, Kiyomitsu Onodera:
High-speed GaAs MESFET Digital IC Design for Optical Communication Systems.
1-5 BibTeX
- Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani:
Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications.
7-12 BibTeX
- Simon Cimin Li, Reggie Chien, Jerry Chien, Kaung-Long Lin:
A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower.
13-18 BibTeX
Session 1B:
Hardware/Software Codesign I
Session 1C:
Technology CAD for Interconnections and Environments
Session 1D:
(Design General Manager Panel) Design Technology Challenges in the Design Productivity Crisis
Session 2A:
Combinational Logic Synthesis
Session 2B:
Compiler for Embedded Processors
Session 2C:
Technology CAD for Lowest Level Design
- Morikazu Tsuno, Masato Suga, Masayasu Tanaka, Kentaro Shibahara, Michiko Miura-Mattausch, Masataka Hirose:
Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET's.
111-116 BibTeX
- Seiichiro Yamaguchi, Hiroshi Goto:
Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be Made.
117-121 BibTeX
- Ute Feldmann, R. Kakoschke, Michiko Miura-Mattausch, G. Schraud:
Concurrent Technology, Device, and Circuit Development for EEPROMs.
123-128 BibTeX
- Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori:
TCAD/DA for MPU and ASIC Development.
129-134 BibTeX
Session 2D (Panel & Embedded Tutorial):
Coupling of Synthesis and Layout:
Challenges and Solutions
- Massoud Pedram:
Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial).
137-142 BibTeX
Session 3A:
DSP System Design
Session 3B:
System Simulation
Session 3C:
Asynchronous Logic Synthesis
Session 3D:
(Invited Talks) Design and EDA Road Map
Session 4A:
Design for Testability
Session 4B:
Model Checking:
Its Basics and Reality
Session 4C:
Pass Transister Logic
Session 4D (Panel Discussion):
Upcoming Deep Sub Micron EDA Tool Problem
Session 5A:
Towards New EDA Standards
- Dinesh R. Bettadapur:
Software Licensing Models in the EDA Industry.
235-239 BibTeX
- Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi:
Pre-layout Delay Calculation Specification for CMOS ASIC Libraries.
241-248 BibTeX
- Donald Cottrell, David Mallis, Joseph Morrell:
CHDStd - A Model for Deep Submicron Design Tools.
249-255 BibTeX
- S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams:
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis.
257-260 BibTeX
- Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki:
ATM Cell Modelling using Objective VHDL.
261-264 BibTeX
Session 5B:
High-Level and System-Level Synthesis
Session 5C:
Performance Driven Layout
- Jinan Lou, Amir H. Salek, Massoud Pedram:
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits.
295-300 BibTeX
- Susumu Kobayashi, Masato Edahiro, Mikio Kubo:
Scan-chain Optimization Algorithms for Multiple Scan-paths.
301-306 BibTeX
- Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design.
307-312 BibTeX
- Jaewon Oh, Massoud Pedram:
Power Reduction in Microprocessor Chips by Gated Clock Routing.
313-318 BibTeX
Session 5D (Special Session):
University LSI Design Contest
- Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor.
319-320 BibTeX
- Tohru Ishihara, Hiroto Yasuura:
Power-Pro: Programmable Power Management Architecture.
321-322 BibTeX
- Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture.
323-324 BibTeX
- Jin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Nam, Chang-Ho Ryu, Jang-Ho Cho, Chong-Min Kyung:
Metacore: A Configurable and Instruction Level Extensible DSP Core.
325-326 BibTeX
- Ho Keun Jang:
A Design of Sound Synthesis IC.
327-328 BibTeX
- Se Young Eun, Myung Hoon Sunwoo:
An Effcient 2-D Convolver Chip for Real Time Image Processing.
329-330 BibTeX
- Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda:
FPGA for High-Performance Bit-Serial Pipeline Datapath.
331-332 BibTeX
- K. Hirano, T. Ono, Hiroyuki Kurino, Mitsumasa Koyanagi:
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory.
333-334 BibTeX
- M. Bickerstaff, T. Arivoli, Philip J. Ryan, Neil Weste, David J. Skellern:
A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter.
335-336 BibTeX
- Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
337-338 BibTeX
- Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa:
A CMOS Smart Image Sensor LSI for Focal-Plane Compression.
339-340 BibTeX
- Changsik Yoo, Wonchan Kim:
A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS.
341-342 BibTeX
- Takayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hatori:
Motion Adaptive Image Sensor.
343-344 BibTeX
Session 6A:
Digital PLL & Timing Design
Session 6B:
Hardware/Software Codesign II
Session 6C:
Layout Optimization and Verification
Session 6D (Invited Talk & Embedded Tutorial):
Interconnections and Packaging for High Speed and High Frequency PCB/MCM
Session 7A:
High-Performance CMOS Circuits
Session 7B:
Decision Diagrams
Session 7C:
Reconfigurable Systems
Session 7D (Panel Discussion):
Asian-Pacific LSI Business in the 21st Century
Session 8A:
Testing
Session 8B:
Analog CAD
Session 8C:
Physical Design for FPGA
- Rongzheng Zhou, Jiarong Tong, Pushan Tang:
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm.
513-518 BibTeX
- Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.
519-526 BibTeX
- Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki, Akihiro Tsutsui:
An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing Resources.
527-533 BibTeX
- Jiaofeng Pan, Yu-Liang Wu, C. K. Wong:
On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures.
535-540 BibTeX
Session 8D (Panel & Embedded Tutorial):
The Next-Generation System Level Design Language
Session 9A:
Analog HDL
- C.-J. Richard Shi:
Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial).
543 BibTeX
Session 9B:
System-Level Power Minimization
Session 9C:
Floorplannning
Session 9D (Invited Talks):
LSI Designs in Multimedia Era
Copyright © Sat May 16 22:58:44 2009
by Michael Ley (ley@uni-trier.de)
