36. ISMVL 2006:
Singapore
36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore.
IEEE Computer Society 2006, ISBN 0-7695-2532-6 BibTeX
Introduction
Session 1:
Invited Address
Session 2:
Circuits I
Session 3:
Algebra and Logic
Session 4:
Circuits II
- Tsutomu Sasao, Jon T. Butler:
Implementation of Multiple-Valued CAM Functions by LUT Cascades.
11
Electronic Edition (link) BibTeX
- Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu:
The new architecture of radix-4 Chinese abacus adder.
12
Electronic Edition (link) BibTeX
- Haque Mohammad Munirul, Michitaka Kameyama:
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.
13
Electronic Edition (link) BibTeX
- Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.
14
Electronic Edition (link) BibTeX
- los Roberto Mingoto Jr.:
A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors.
15
Electronic Edition (link) BibTeX
Session 5:
Invited Address
Session 6:
Circuits III
Session 7:
Algebra and Clones
Session 8:
Systems and Satisfiability
Session 9:
Decision Diagrams and Decision Trees
Session 10:
Quantum Logic and Spectral Techniques
Copyright © Sat May 16 23:25:54 2009
by Michael Ley (ley@uni-trier.de)
