ISVLSI 2006:
Karlsruhe,
Germany
2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany.
IEEE Computer Society 2006, ISBN 0-7695-2533-4 BibTeX
Keynotes
Intellectual Property and Design
- Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin:
Floorplanning Based on Particle Swarm Optimization.
7-11
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- Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan:
Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.
12-17
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- Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani:
Adaptive Porting of Analog IPs with Reusable Conservative Properties.
18-23
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- Wael Adi, Rolf Ernst, Bassel Soudan, Abdulrahman Hanoun:
VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography.
24-32
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Physical Design
High Performance Circuits
Reconfigurable Systems Integration
- Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson:
Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip Technology.
85-90
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- Rahul Jain, Anindita Mukherjee, Kolin Paul:
Defect-Aware Design Paradigm for Reconfigurable Architectures.
91-96
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- Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker:
New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits.
97-102
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- Victor Aken Ova, Resve Saleh:
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm.
103-108
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- Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Two-Level Reconfigurable Architecture.
109-116
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Mixed-Signal Design and Analysis
Test and Verification
- Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
Verification of Scheduling in High-level Synthesis.
141-146
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- Ming Li, Wen-Ben Jone, Qing-An Zeng:
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing.
147-152
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- Xiaoyu Ruan, Rajendra S. Katti:
An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip.
153-158
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- Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker:
Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.
159-166
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Low Power System Design
System-on-Chip
- Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi:
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.
193-198
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- Esmail Amini, Mehrdad Najibi, Hossein Pedram:
Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating.
193-199
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- Zhonghai Lu, Bei Yin, Axel Jantsch:
Connection-oriented Multicasting in Wormhole-switched Networks on Chip.
205-2110
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- Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Pascal T. Wolkotte:
A Virtual Channel Network-on-Chip for GT and BE traffic.
211-216
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- Ethiopia Nigussie, Juha Plosila, Jouni Isoaho:
Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.
217-224
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Nano Electronics
- Eric Rachlin, John E. Savage:
Nanowire Addressing in the Face of Uncertainty.
225-230
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- Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita:
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.
231-236
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- Jialin Mi, Chunhong Chen:
Finite State Machine Implementation with Single-Electron Tunneling Technology.
237-241
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- Xiaobo Sharon Hu, Michael Crocker, Michael T. Niemier, Minjun Yan, Gary H. Bernstein:
PLAs in Quantum-dot Cellular Automata.
242-250
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Reconfigurable System Design and Technologies
- Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker:
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
251-256
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- Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer:
Regular Routing Architecture for a LUT-based MPGA.
257-262
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- Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
A new Multilevel Hierarchical MFPGA and its suitable configuration tools.
263-268
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- Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
New non-volatile FPGA concept using Magnetic Tunneling Junction.
269-276
Electronic Edition (link) BibTeX
Complexity and System Organization
System Level and Circuit Analysis
System Level Design
Power Aware VLSI Design
VLSI Circuits and Optimization
VLSI Circuits and Technologies
Poster Papers
- Ali Jahanian, Morteza Saheb Zamani:
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits.
411-415
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- Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam:
Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.
416-417
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- Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar:
Towards a Faster Simulation of SystemC Designs.
418-419
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- Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi:
An Optimized BIST Architecture for FPGA Look-Up Table Testing.
420-421
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- Suresh Srinivasan, Narayanan Vijaykrishnan:
Variation Aware Placement for FPGAs.
422-423
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- Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares:
A Regular Layout Approach for ASICs.
424-425
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- José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes:
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
426-427
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- Johannes Grad, James E. Stine:
Dual-Mode High-Speed Low-Energy Binary Addition.
428-429
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- Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
430-431
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- Krzysztof Kosciuszkiewicz, Krzysztof Kepa, Fearghal Morgan:
Transparent Management of Reconfigurable Hardware in Embedded Operating Systems.
432-433
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- Alisson V. De Brito, Elmar U. K. Melcher, Wilson Rosas:
An open-source tool for simulation of partially reconfigurable systems using SystemC.
434-435
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- Florent Berthelot, Fabienne Nouvel:
Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation.
436-437
Electronic Edition (link) BibTeX
- David Fang, Filipp Akopyan, Rajit Manohar:
Self-Timed Thermally-Aware Circuits.
438-439
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- Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi:
A New Protocol Stack Model for Network on Chip.
440-441
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- Jun Zhou, David Kinniment, Gordon Russell, Alexandre Yakovlev:
A Robust Synchronizer.
442-443
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- T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J. H. Han:
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems.
444-445
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- Josef Haid, Dietmar Scheiblhofer:
Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems.
446-447
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- Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir:
Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems.
448-449
Electronic Edition (link) BibTeX
- Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran:
Compiler-Directed Management of Leakage Power in Software-Managed Memories.
450-451
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- Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin:
A Parallel Architecture for Hardware Face Detection.
452-453
Electronic Edition (link) BibTeX
- Ciaran Toal, Sakir Sezer, Xin Yang:
A VLSI GFP Frame Delineation Circuit.
454-455
Electronic Edition (link) BibTeX
- Itisha Chanodia, Dimitrios Velenis:
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks.
456-457
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Copyright © Sat May 16 23:26:34 2009
by Michael Ley (ley@uni-trier.de)
