DSD 2002:
Dortmund,
Germany
2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany.
IEEE Computer Society 2002, ISBN 0-7695-1790-0 BibTeX
Plenary - Keynote Session I
Processor and Memory Architectures
Partitioning and Decomposition
- Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst:
Recursive Bi-Partitioning of Netlists for Large Number of Partitions.
38-44
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- Ivan Milentijevic, Vladimir Ciric, Teufik Tokic, Oliver Vojinovic:
Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor.
45-52
Electronic Edition (link) BibTeX
- Yinshui Xia, A. E. A. Almaini:
Best Polarity for Low Power XOR Gate Decomposition.
53-59
Electronic Edition (link) BibTeX
- José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design.
60-69
Electronic Edition (link) BibTeX
Special Architectures
- Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses:
A Flexible Architecture for H.263 Video Coding.
70-77
Electronic Edition (link) BibTeX
- Omar Mansour, Egbert Molenkamp, Thijs Krol:
The Synthesis of a Hardware Scheduler for Non-Manifest Loops.
78-85
Electronic Edition (link) BibTeX
- Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen:
Configurable Memory Organisation for Communication Applications.
86-93
Electronic Edition (link) BibTeX
- Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke:
Enhanced Reusability for SoC-Based HW/SW Co-Design.
94-101
Electronic Edition (link) BibTeX
System Specification and Modelling
Parallel Processor Architectures
Verification and Test
- Josef Strnadel, Zdenek Kotásek:
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.
166-173
Electronic Edition (link) BibTeX
- Roman Goot, Ilya Levin, Sergei Ostanin:
Fault Latencies of Concurrent Checking FSMs.
174-179
Electronic Edition (link) BibTeX
- Paul Amblard, Fabienne Lagnier, Michel Lévy:
Using Formal Tools to Study Complex Circuits Behaviour.
180-186
Electronic Edition (link) BibTeX
- André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng:
Integrated Design and Test Generation Under Internet Based Environment MOSCITO.
187-195
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Plenary - Keynote Session II
Filter and Arithmetic Circuits
Circuit Synthesis and Optimisation
Reconfigurable Computing Architectures
High Level Synthesis
Panel - Systems-on-Chip
Poster Session
- Zeljko Vujovic:
Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers.
332-336
Electronic Edition (link) BibTeX
- Rolf Drechsler, Daniel Große:
Reachability Analysis for Formal Verification of SystemC.
337-340
Electronic Edition (link) BibTeX
- Toshinori Sato, Itsujiro Arita:
Simplifying Instruction Issue Logic in Superscalar Processors.
341-346
Electronic Edition (link) BibTeX
- Martin Feldhofer, Thomas Trathnigg, Bernd Schnitzer:
A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography.
347-350
Electronic Edition (link) BibTeX
- Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo:
Low Power Strategy for a TFT Controller.
351-354
Electronic Edition (link) BibTeX
- Khushwinder Jasrotia, Jianwen Zhu:
Hardware Implementation of a Memory Allocator.
355-358
Electronic Edition (link) BibTeX
- Mariusz Chyzy, Witold Kosinski:
Evolutionary Algorithm for State Assignment of Finite State Machines.
359-363
Electronic Edition (link) BibTeX
Specification and Modelling
Synthesis and Algorithms
Copyright © Sat May 16 23:07:28 2009
by Michael Ley (ley@uni-trier.de)
