| |
| 2001 | ||
|---|---|---|
| 2 | EE | Peer Johannsen: BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction. CAV 2001: 373-377 |
| 1 | Peer Johannsen, Rolf Drechsler: Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374 | |
| 1 | Rolf Drechsler | [1] |