5. MEMOCODE 2007: Nice, France

• Ivan Radojevic, Zoran A. Salcic, Partha S. Roop:
  McCharts and Multiclock FSMs for modeling large scale systems. 3-12
  Electronic Edition (link) BibTeX
• Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalkar, Luca P. Carloni:
  Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design. 13-22
  Electronic Edition (link) BibTeX
• Xavier Leroy:
  Formal verification of an optimizing compiler. 25
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• Yi Lv, Huimin Lin, Hong Pan:
  Computing Invariants for Parameter Abstraction. 29-38
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• Rathijit Sen, Y. N. Srikant:
  Executable Analysis using Abstract Interpretation with Circular Linear Progressions. 39-48
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• Nirav Dave, Arvind, Michael Pellauer:
  Scheduling as Rule Composition. 51-60
  Electronic Edition (link) BibTeX
• Deepak Mathaikutty, Sandeep K. Shukla:
  Type Inference for IP Composition. 61-70
  Electronic Edition (link) BibTeX
• Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks:
  From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. 71-80
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• Edgar G. Daylight, Sandeep K. Shukla:
  Local Causal Reasoning of a Safety-Critical Subway System. 83-84
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• Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler:
  Multi-Level Assertion-Based Design. 85-86
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• Youngseok Oh, Danhyung Lee, Sungwon Kang, Jihyun Lee:
  Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded Systems. 87-88
  Electronic Edition (link) BibTeX
• Forrest Brewer, James C. Hoe:
  MEMOCODE 2007 Co-Design Contest. 91-94
  Electronic Edition (link) BibTeX
• Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla:
  VT Matrix Multiply Design for MEMOCODE '07. 95-96
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• Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan:
  Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. 97-100
  Electronic Edition (link) BibTeX
• Bernhard Niemann, Christian Haubelt:
  Towards a Unified Execution Model for Transactions in TLM. 103-112
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• Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva:
  Towards Equivalence Checking Between TLM and RTL Models. 113-122
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• Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin:
  Verification Driven Formal Architecture and Microarchitecture Modeling. 123-132
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• Bertrand Meyer:
  Proving What Programs Do Not. 135
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• Bart D. Theelen, Oana Florescu, Marc Geilen, Jinfeng Huang, P. H. A. van der Putten, Jeroen Voeten:
  Software/Hardware Engineering with the Parallel Object-Oriented Specification Language. 139-148
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• Wu Jigang, Thambipillai Srikanthan, Guang Chen:
  One-dimensional Search Algorithms for Hardware/Software Partitioning. 149-158
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• Proshanta Saha, Tarek A. El-Ghazawi:
  A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems. 159-168
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• Geoffrey M. Brown, Lee Pike:
  Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols. 171-180
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• Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
  Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. 181-187
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• Hana Chockler, Ofer Strichman:
  Easier and More Informative Vacuity Checks. 189-198
  Electronic Edition (link) BibTeX
• Byron Cook:
  Bringing Hardware and Software Closer Together with Termination Analysis. 201
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