26. ISMVL 1996: Santiago de Compostela, Spain

26th IEEE International Symposium on Multiple-Valued Logic (ISMVL 1996), May 19-31, 1996, Santiago de Compostela, Spain, Proceedings. IEEE Computer Society, 1996, online publication: http://computer.org/proceedings/ismvl/7392/7392toc.htm

Keynote Address I

Claudi Alsina:
As You Like Them: Connectives in Fuzzy Logic. 2-
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Logic Design I

Rolf Drechsler:
Verification of Multi-Valued Logic Networks. 10-15
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Zeljko Zilic, Zvonko G. Vranesic:
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. 16-23
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Susanto Rahardja, Bogdan J. Falkowski:
Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions. 24-
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Logic I

Antonio di Nola:
Non-Archimedean Models of Lukasiewicz Logic. 32-36
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Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono:
A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. 37-42
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Robert J. Bignall, Matthew Spinks:
Propositional Skew Boolean Logic. 43-
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Fault Modeling, Fault Diagnosis

L. J. de Miguel, Margarita Mediavilla, Jose Ramón Perán González:
Fault Diagnosis System Based on Sensitivity Analysis and Fuzzy Logic. 50-55
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Elena Dubrova, Jon C. Muzio:
Testability of Generalized Multiple-Valued Reed-Muller Circuits. 56-61
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Mou Hu:
Design of One-Vector Testable Binary Systems Based on Ternary Logic. 62-
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Devices

Takao Waho, Kevin J. Chen, Masafumi Yamamoto:
A Literal Gate Using Resonant-Tunneling Devices. 68-73
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Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu:
A Multiple-Valued Ferroelectric Content-Addressable Memory. 74-79
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Lutz J. Micheel, Hans L. Hartnagel:
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. 80-85
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K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic:
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. 86-
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Circuits, Logic Design I

Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller:
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. 92-97
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Mostafa H. Abd-El-Barr, M. N. Hasan:
New MVL-PLA Structures Based on Current-Mode CMOS Technology. 98-103
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Masami Nakajima, Michitaka Kameyama:
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. 104-109
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Come Rozon:
On the Use of VHDL as a Multi-Valued Logic Simulator. 110-
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Logic II

Reiner Hähnle:
Commodious Axiomatization of Quantifiers in Multiple-Valued Logic. 118-123
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Weiru Liu:
The Incidence Propagation Method. 124-129
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Herman Akdag, Myriam Mokhtari:
Approximative Conjunctions Processing by Multi-Valued Logic. 130-135
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Matthias Baaz, Christian G. Fermüller:
Intuitionistic Counterparts of Finitely-Valued Logics. 136-
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Special Session: Helena Rasiowa, In Memoriam

G. Malinowski:
Helena Rasiowa - A View of the Academic Trajectory and the Influence upon Polish and the International Scientific Community. 144-146
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Josep Maria Font:
On the Contributions of Helena Rasiowa to Mathematical Logic. 147
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Ton Sales:
From Pure to Approximate Logic. 148-
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Algebra I

V. Cutello, E. Molina, J. Montero:
Associativeness versus Recursiveness. 154-159
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Hassan Bezzazi, Ramón Pino Pérez:
Rational Transitivity and its Models. 160-165
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Dan A. Simovici, Corina Reischer:
Several Remarks on the Complexity of Set-Valued Switching Functions. 166-
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Artificial Intelligence, Reasoning

Alberto Bugarín, Purificación Cariñena, Manuel Fernández Delgado, Senén Barro:
Petri Net Representation of Fuzzy Reasoning under Incomplete Information. 172-177
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S. Lehmke:
Weight Structures for Approximate Reasoning with Weighted Expressions. 178-183
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Salem Benferhat, Didier Dubois, Henri Prade:
Reasoning in Inconsistent Stratified Knowledge Bases. 184-
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Keynote Address II

Lotfi A. Zadeh:
Inference in Fuzzy Logic via Generalized Constraint Propagation. 192-
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Algebra II

Helmut Thiele:
On Isomorphisms between the Lattice of Tolerance Relations and Lattices of Clusterings. 198-202
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Ivo G. Rosenberg:
An Algebraic Approach to Hyperalgebras. 203-
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Soft Computing

Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. 210-215
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Wenjun Wang, Claudio Moraga:
Design of Multivalued Circuits using Genetic Algorithms. 216-
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Circuits, Logic Design II

Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
Quaternary Universal-Literal CAM for Cellular Logic Image Processing. 224-229
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Hao Tang, Hung Chang Lin:
Multi-Valued Decoder Based on Resonant Tunneling Diodes in Current Tapping Mode. 230-
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Decision Diagrams

Jon T. Butler, J. L. Nowlin, Tsutomu Sasao:
Planarity in ROMDD's of Multiple-Valued Symmetric Functions. 236-241
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D. Michael Miller, Noriaki Muranaka:
Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. 242-247
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Tsutomu Sasao, Jon T. Butler:
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. 248-254
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Bogdan J. Falkowski, Susanto Rahardja:
Complex Spectral Decision Diagrams. 255-
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Algebra III

B. A. Romov:
Polynomial Completeness Criteria in Finite Boolean Algebras. 262-266
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Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar:
Technique of Computing Logic Derivatives for MVL-Functions. 267-272
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Lucien Haddad, Jean Fugère:
On the Lattice of Partial Clones on a Finite Set. 273-278
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F. Sokhatsky:
The Deepest Repetition-Free Decompositions of Non-Singular Functions of Finite-Valued Logics. 279-
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Logic III

Stefan Gerberding:
DT - An Automated Theorem Prover for Multiple-Valued First-Order Predicate Logics. 284-289
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Kyoichi Nakashima, Y. Nakamura, Noboru Takagi:
Logic Expressions of Monotonic Multiple-Valued Functions. 290-295
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Grant Pogosyan:
Efficiently Irreducible Bases in Multiple-Valued Logic. 296-301
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Elena N. Zaitseva, Tatiana Kalganova, Evgeny G. Kochergov:
Logical Not Polynomial Forms to Represent Multiple-Valued Functions. 302-307
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