33. ISMVL 2003:
Tokyo,
Japan
33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan.
IEEE Computer Society 2003, ISBN 0-7695-1918-0 BibTeX
@proceedings{DBLP:conf/ismvl/2003,
title = {33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL
2003), 16-19 May 2003, Tokyo, Japan},
booktitle = {ISMVL},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-1918-0},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Invited Address
Logic Design
Functional Expressions
Fuzzy Logic
LSI Design
- Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi:
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms.
91-98
Electronic Edition (IEEE Computer Society DL) BibTeX
- Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama:
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
99-104
Electronic Edition (IEEE Computer Society DL) BibTeX
- E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson:
MVL circuit design and characterization at the transistor level using SUS-LOC.
105-110
Electronic Edition (IEEE Computer Society DL) BibTeX
- Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon:
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits.
111-116
Electronic Edition (IEEE Computer Society DL) BibTeX
- Gi Soo Na, Sang Wan Kim, Jai Sock Choi, Heung-Soo Kim:
Recursive Evaluation of the Generalized Reed-Muller Coefficients.
117-
Electronic Edition (IEEE Computer Society DL) BibTeX
Logic Design II
Logics and Algebras
Invited Address
LSI Circuits
Decision Diagrams I
Nano Technology
- Hiroshi Inokawa, Yasuo Takahashi:
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.
259-266
Electronic Edition (IEEE Computer Society DL) BibTeX
- Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park:
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
267-272
Electronic Edition (IEEE Computer Society DL) BibTeX
- Tetsuya Uemura, Masafumi Yamamoto:
Proposal of Four-Valued MRAM based on MTJ/RTD Structure.
273-
Electronic Edition (IEEE Computer Society DL) BibTeX
Modeling and Simulation
Clone Theory
Spectral Techniques
Invited Address
Applications
Decision Diagrams II
Copyright © Sat May 16 23:25:54 2009
by Michael Ley (ley@uni-trier.de)
