| 2008 |
|---|
| 10 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Siamak Mohammadi:
Graph based test case generation for TLM functional verification.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 288-295 (2008) |
| 2007 |
|---|
| 9 | EE | Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Majid Nabi,
Simak Mohammadi:
System Level Voltage Scheduling Technique Using UML-RT Model.
AICCSA 2007: 500-505 |
| 8 | EE | Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Mohammad Reza Kakoee,
Saeed Safari:
Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.
AICCSA 2007: 528-534 |
| 7 | EE | Alireza Aminlou,
Maryam Homayouni,
Mohammad Hossein Neishaburi,
Siamak Mohammadi:
A Superior Low Complexity Rate Control Algorithm.
AICCSA 2007: 726-729 |
| 6 | | Mohammad Hossein Neishaburi,
Mohammad Reza Kakoee,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
DDECS 2007: 247-250 |
| 5 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Siamak Mohammadi:
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.
DSD 2007: 157-164 |
| 4 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
On-Chip Verification of NoCs Using Assertion Processors.
DSD 2007: 535-538 |
| 3 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Zainalabedin Navabi,
Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
IOLTS 2007: 205-206 |
| 2 | EE | Masoud Daneshtalab,
A. Pedram,
Mohammad Hossein Neishaburi,
M. Riazati,
Ali Afzali-Kusha,
Simak Mohammadi:
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
VLSI Design 2007: 546-550 |
| 1 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
VTS 2007: 243-248 |
