2008 |
18 | EE | Mohammad Hosseinabady,
Jose Nunez-Yanez:
Fault-tolerant dynamically reconfigurable NoC-based SoC.
ASAP 2008: 31-36 |
17 | EE | Mohammad Hosseinabady,
Mohammad Reza Kakoee,
Jimson Mathew,
Dhiraj K. Pradhan:
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
DATE 2008: 1370-1373 |
16 | EE | Jimson Mathew,
Jawar Singh,
Abusaleh M. Jabir,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS 2008: 1684-1687 |
15 | EE | Mohammad Hosseinabady,
Shervin Sharifi,
Fabrizio Lombardi,
Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers 57(3): 316-328 (2008) |
2007 |
14 | EE | Mohammad Hosseinabady,
Atefe Dalirsani,
Zainalabedin Navabi:
Using the inter- and intra-switch regularity in NoC switch testing.
DATE 2007: 361-366 |
13 | EE | Jawar Singh,
Jimson Mathew,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Single Event Upset Detection and Correction.
ICIT 2007: 13-18 |
12 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Zainalabedin Navabi,
Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
IOLTS 2007: 205-206 |
11 | EE | Atefe Dalirsani,
Mohammad Hosseinabady,
Zainalabedin Navabi:
An Analytical Model for Reliability Evaluation of NoC Architectures.
IOLTS 2007: 49-56 |
10 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
VTS 2007: 243-248 |
9 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
8 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
CoRR abs/0710.4653: (2007) |
2006 |
7 | EE | Mohammad Hosseinabady,
Abbas Banaiyan,
Mahdi Nazm Bojnordi,
Zainalabedin Navabi:
A concurrent testing method for NoC switches.
DATE 2006: 1171-1176 |
6 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Giorgio Di Natale,
Stefano Di Carlo,
Alfredo Benso,
Paolo Prinetto:
Single-Event Upset Analysis and Protection in High Speed Circuits.
European Test Symposium 2006: 29-34 |
5 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electronics 2(3): 477-487 (2006) |
2005 |
4 | EE | Pejman Lotfi-Kamran,
Mohammad Hosseinabady,
Hamid Shojaei,
Mehran Massoumi,
Zainalabedin Navabi:
TED+: a data structure for microprocessor verification.
ASP-DAC 2005: 567-572 |
3 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
DATE 2005: 846-851 |
2003 |
2 | EE | Shervin Sharifi,
Mohammad Hosseinabady,
Pedram A. Riahi,
Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
DFT 2003: 352-360 |
1 | | Shervin Sharifi,
Mohammad Hosseinabady,
Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
VLSI-SOC 2003: 215-220 |