| |
| 1999 | ||
|---|---|---|
| 4 | EE | Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue: A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. Asian Test Symposium 1999: 309-314 |
| 1998 | ||
| 3 | Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara: Partial Scan Design Methods Based on Internally Balanced Structure. ASP-DAC 1998: 211-216 | |
| 2 | EE | Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara: Partial scan design methods based on internally balanced structure. Systems and Computers in Japan 29(10): 26-35 (1998) |
| 1997 | ||
| 1 | EE | Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki: A sequential circuit structure with combinational test generation complexity and its application. Systems and Computers in Japan 28(11): 11-21 (1997) |
| 1 | Hideo Fujiwara | [1] [2] [3] [4] |
| 2 | Tomoo Inoue | [2] [3] [4] |
| 3 | Satoshi Ohtake | [1] |