IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 5

Volume 5, Number 1, January 1986

• Ping Yang, Dale E. Hocevar, Paul F. Cox, Charles F. Machala III, Pallab K. Chatterjee:
  An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design. 5-14
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• Norm Herr, John J. Barnes:
  Statistical Circuit Simulation Modeling of CMOS VLSI. 15-22
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• M. L. Stein:
  An Efficient Method of Sampling for Statistical Circuit Design. 23-29
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• M. A. Styblinski:
  Problems of Yield Gradient Estimation for Truncated Probability Density Functions. 30-38
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• Darrell Makarenko, John Tartar:
  A Statistical Analysis of PLA Folding. 39-51
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• Sarma Sastry, Alice C. Parker:
  Stochastic Models for Wireability Analysis of Gate Arrays. 52-65
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• Costas J. Spanos, Stephen W. Director:
  Parameter Extraction for Statistical IC Process Characterization. 66-78
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• M. A. Styblinski, Leszek J. Opalski:
  Algorithms and Software Tools for IC Yield Optimization Based on Fundamental Fabrication Parameters. 79-89
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• J. P. Spoto, W. T. Coston, C. Paul Hernandez:
  Statistical Integrated Circuit Design and Characterization. 90-103
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• Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
  A Methodology for Worst-Case Analysis of Integrated Circuits. 104-113
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• Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director:
  VLSI Yield Prediction and Estimation: A Unified Framework. 114-130
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• David C. Riley, Alberto L. Sangiovanni-Vincentelli:
  Models for a New Profit-Based Methodology for Statistical Design of Integrated Circuits. 131-169
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• Shui-Jinn Wang, Jau-Yien Lee, Chun-Yen Chang:
  An Efficient and Reliable Approach for Semiconductor Device Parameter Extraction. 170-179
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• Kung-Chao Chu, John P. Fishburn, Peter Honeyman, Y. Edmund Lien:
  A Database-Driven VLSI Design System. 180-187
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• Tzu-Mu Lin, Carver Mead:
  A Hierarchical Timing Simulation Model. 188-197
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• Richard C. Jaeger:
  Computer-Aided Design of One-Dimensional MOSFET Impurity Profiles. 198-203
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• Wieslaw Kuzmicz:
  Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions. 204-214
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• R. H. Uebbing, Masao Fukuma:
  Process-Based Three-Dimensional Capacitance Simulation -- TRICEPS. 215-220
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• J. W. Greene, Kenneth J. Supowit:
  Simulated Annealing Without Rejected Moves. 221-228
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• Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin:
  McBOOLE: A New Procedure for Exact Logic Minimization. 229-238
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• Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Correction to "Optimal State Assignment for Finite State Machines". 239-239
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Volume 5, Number 2, April 1986

• Alexander Iosupovici:
  A Class of Array Architectures for Hardware Grid Routers. 245-255
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• P. A. Ruetz, Stephen P. Pope, Robert W. Brodersen:
  Computer Generation of Digital Filter Banks. 256-265
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• Andrzej Peczalski, Michael S. Shur, Choong H. Hyun, Kang W. Lee, Tho Truong Vu:
  Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic. 266-273
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• John P. Hayes:
  Digital Simulation with Multiple Logic Values. 274-283
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• Choong H. Hyun, Michael S. Shur, Nicholas C. Cirillo Jr.:
  Simulation and Design Analysis of (A1Ga)As/GaAs MODFET Integrated Circuits. 284-292
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• M. Sugimoto, M. Fukuma:
  Standard Description Form for Device Characteristics in VLSI's. 293-302
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• Nripendra N. Biswas:
  Computer-Aided Minimization Procedure for Boolean Functions. 303-304
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• Charles A. Zukowski:
  Relaxing Bounds for Linear RC Mesh Circuits. 305-312
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• Norio Kuji, Teruo Tamama, M. Nagatani:
  FINDER: A CAD System-Based Electron Beam Tester for Fault Diagnosis of VLSI Circuits. 313-319
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• W. Maes, Kristin M. De Meyer, Luc H. Dupas:
  SIMPAR: A Versatile Technology Independent Parameter Extraction Program Using a New Optimized Fit-Strategy. 320-325
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• C. C. Moglestue:
  A Self-Consistent Monte Carlo Particle Model to Analyze Semiconductor Microcomponents of any Geometry. 326-345
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• Leszek J. Opalski, M. A. Styblinski:
  Generalization of Yield Optimization Problem: Maximum Income Approach. 346-360
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Volume 5, Number 3, July 1986

• S. Onga, M. Konaka, A. Ohmichi, K. Kanaka, R. Dang:
  A Composite Two-Dimensional Process/Device Simulation System (TOPMODE) and its Application for Total Process Designing in Submicron VLSI MOS Device Phase. 365-370
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• J. Katzenelson, E. Weitz:
  VLSI Simulation and Data Abstractions. 371-378
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• Chia-Jeng Tseng, Daniel P. Siewiorek:
  Automated Synthesis of Data Paths in Digital Systems. 379-395
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• Ilan Y. Spillinger, Gabriel M. Silberman:
  Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. 396-404
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• Roger D. Chamberlain, Mark A. Franklin:
  Collecting Data About Logic Simulation. 405-412
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• Randy Lee Brown:
  Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees. 413-419
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• Robert Michael Owens, Mary Jane Irwin:
  A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. 420-428
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• Gregory J. Fisher, J. Alvin Connelly:
  Modeling Time-Dependent Elements for SPICE Transient Analyses. 429-432
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• Sun Young Hwang, Robert W. Dutton, Tom Blank:
  A Best-First Search Algorithm for Optimal PLA Folding. 433-442
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• U. V. Wali, R. N. Pal, B. Chatterjee:
  Compact Modified Nodal Approach for Switched-Capacitor Network Analysis. 443-447
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Volume 5, Number 4, October 1986

• Stephen D. Posluszny:
  SLS: An Advanced Symbolic Layout System for Bipolar and FET Design. 450-458
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• Howard H. Chen, Ernest S. Kuh:
  Glitter: A Gridless Variable-Width Channel Router. 459-465
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• Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki:
  A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. 466-476
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• David P. La Potin, Stephen W. Director:
  Mason: A Global Floorplanning Approach for VLSI Design. 477-489
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• Martin L. Resnick:
  SPARTA: A System Partitioning Aid. 490-498
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• Claudio Turchetti, P. Prioretti, Guido Masetti, E. Profumo, Massimo Vanzi:
  A Meyer-Like Approach for the Transient Analysis of Digital MOS IC's. 499-507
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• Rahul Razdan, Andrzej J. Strojwas:
  A Statistical Design Rule Developer. 508-520
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• Kenneth S. Kundert, Alberto L. Sangiovanni-Vincentelli:
  Simulation of Nonlinear Circuits in the Frequency Domain. 521-535
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• David Tsao, Chin-Fu Chen:
  A Fast-Timing Simulator for Digital MOS Circuits. 536-540
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• D. M. H. Walker, Stephen W. Director:
  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. 541-556
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• Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham:
  FAUST: An MOS Fault Simulator with Timing Information. 557-563
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• Ki Soo Hwang, M. Ray Mercer:
  Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. 564-572
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• Hasan Elhuni, Anastasios Vergis, Larry L. Kinney:
  C-Testability of Two-Dimensional Iterative Arrays. 573-581
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• Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel:
  Synthesis and Optimization of Multilevel Logic under Timing Constraints. 582-596
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• Giovanni De Micheli:
  Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros. 597-616
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• Prathima Agrawal:
  Concurrency and Communication in Hardware Simulators. 617-623
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• T. Shima:
  Table Lookup MOSFET Capacitance Model for Short-Channel Devices. 624-632
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• Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli:
  PLATYPUS: A PLA Test Pattern Generation Tool. 633-644
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• Jeffrey Y.-F. Tang, Steven E. Laux:
  MONTE: A Program to Simulate the Heterojunction Devices in Two Dimensions. 645-652
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• Surya Veeraraghavan, Jerry G. Fossum, William R. Eisenstadt:
  SPICE Simulation of SOI MOSFET Integrated Circuits. 653-658
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• Mark Douglas Matson, Lance A. Glasser:
  Macromodeling and Optimization of Digital MOS VLSI Circuits. 659-678
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• Martin D. Giles:
  Ion Implantation Calculations in Two Dimensions Using the Boltzmann Transport Equation. 679-684
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