| 1996 |
|---|
| 5 | EE | Paul R. Stephan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Combinational test generation using satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1167-1176 (1996) |
| 1994 |
|---|
| 4 | EE | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Specification, synthesis, and verification of hazard-free asynchronous circuits.
VLSI Signal Processing 7(1-2): 85-100 (1994) |
| 1993 |
|---|
| 3 | | Paul R. Stephan,
Robert K. Brayton:
Physically Realizable Gate Models.
ICCD 1993: 442-445 |
| 1991 |
|---|
| 2 | | Patrick C. McGeer,
Alexander Saldanha,
Paul R. Stephan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.
ICCAD 1991: 180-183 |
| 1 | | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.
ICCAD 1991: 322-325 |
