Volume 6,
Number 1,
January 1987
- K. C.-K. Weng, Ping Yang, Jue-Hsien Chern:
A Predictor/CAD Model for Buried-Channel MOS Transistors.
4-16
Electronic Edition (link) BibTeX
- C. Andrew Neff, Ravi Nair:
A Ranking Algorithm for MOS Circuit Layouts.
17-21
Electronic Edition (link) BibTeX
- Rajiv Kane, Sartaj K. Sahni:
A Systolic Design-Rule Checker.
22-32
Electronic Edition (link) BibTeX
- Dan I. Moldovan:
ADVIS: A Software Package for the Design of Systolic Arrays.
33-40
Electronic Edition (link) BibTeX
- Zhiping Yu, Robert W. Dutton, Massimo Vanzi:
An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess.
41-45
Electronic Edition (link) BibTeX
- Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori:
Block-Level Hardware Logic Simulation Machine.
46-54
Electronic Edition (link) BibTeX
- Maciej J. Ciesielski, E. Kinnen:
Digraph Relaxation for 2-Dimensional Placement of IC Blocks.
55-66
Electronic Edition (link) BibTeX
- K. C. Chang, David Hung-Chang Du:
Efficient Algorithms for Layer Assignment Problem.
67-78
Electronic Edition (link) BibTeX
- Narsingh Deo, Mukkai S. Krishnamoorthy, Michael A. Langston:
Exact and Approximate Solutions for the Gate Matrix Layout Problem.
79-84
Electronic Edition (link) BibTeX
- Silvano Gai, Fabio Somenzi, M. Spalla:
Fast and Coherent Simulation with Zero Delay Elements.
85-93
Electronic Edition (link) BibTeX
- Kenneth J. Supowit:
Finding a Maximum Planar Subset of a Set of Nets in a Channel.
93-94
Electronic Edition (link) BibTeX
- Sangyong Han, Sartaj K. Sahni:
Layering Algorithms For Single-Row Routing.
95-102
Electronic Edition (link) BibTeX
- Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan:
Linking the Behavioral and Structural Domains of Representation for Digital System Design.
103-110
Electronic Edition (link) BibTeX
- Issac L. Bain, Lance A. Glasser:
Methodology Verification of Hierarchically Described VLSI Circuits.
111-115
Electronic Edition (link) BibTeX
- K. S. Kumar, J. H. Tracey:
Modeling and Description of Processor-Based Systems with DTMSII.
116-127
Electronic Edition (link) BibTeX
- Vasant B. Rao, Timothy N. Trick:
Network Partitioning and Ordering for MOS VLSI Circuits.
128-144
Electronic Edition (link) BibTeX
- K. Komatsu, M. Suzuki:
The Outline Procedure in Pattern Data Preparation for Vector-Scan Electron-Beam Lithography.
145-151
Electronic Edition (link) BibTeX
Volume 6,
Number 2,
March 1987
- Takashi Fujii, Hideya Horikawa, Tohru Kikuno, Noriyoshi Yoshida:
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach.
159-164
Electronic Edition (link) BibTeX
- Ravi Nair:
A Simple Yet Effective Technique for Global Wiring.
165-172
Electronic Edition (link) BibTeX
- Hiroshi Iwai, Mark R. Pinto, Conor S. Rafferty, J. E. Oristian, Robert W. Dutton:
Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances.
173-184
Electronic Edition (link) BibTeX
- A. Akiyama, T. Hosoi, I. Ishihara, S. Matsumoto, T. Niimi:
Computer Simulation of Impurity Diffusion in Semiconductors by the Monte Carlo Method.
185-189
Electronic Edition (link) BibTeX
- David Hung-Chang Du, Oscar H. Ibarra, J. Fernando Naveda:
Single-Row Routing with Crossover Bound.
190-201
Electronic Edition (link) BibTeX
- Kevin S. B. Szabo, James M. Leask, Mohamed I. Elmasry:
Symbolic Layout for Bipolar and MOS VLSI.
202-210
Electronic Edition (link) BibTeX
- Patrick Siarry, L. Bergonzi, Gérard Dreyfus:
Thermodynamic Optimization of Block Placement.
211-221
Electronic Edition (link) BibTeX
- Chin-Long Wey, Fabrizio Lombardi:
On the Repair of Redundant RAM's.
222-231
Electronic Edition (link) BibTeX
- Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose:
Algorithms for an Advanced Fault Simulation System in MOTIS.
232-240
Electronic Edition (link) BibTeX
- T. Watanabe, H. Kitazawa, Y. Sugiyama:
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor.
241-250
Electronic Edition (link) BibTeX
- Ibrahim N. Hajj, Daniel G. Saab:
Switch-Level Logic Simulation of Digital Bipolar Circuits.
251-258
Electronic Edition (link) BibTeX
- Howard Trickey:
Flamel: A High-Level Hardware Compiler.
259-269
Electronic Edition (link) BibTeX
- Nils Hedenstierna, Kjell O. Jeppson:
CMOS Circuit Speed and Buffer Optimization.
270-281
Electronic Edition (link) BibTeX
- Rolf Sundblad, Christer Svensson:
Fully Dynamic Switch-Level Simulation of CMOS Circuits.
282-289
Electronic Edition (link) BibTeX
- Yiu Kei Li, J. P. Robinson:
Space Compression Methods With Output Data Modification.
290-294
Electronic Edition (link) BibTeX
Volume 6,
Number 3,
May 1987
- Masaharu Hirayama:
A Silicon Compiler System Based on Asynchronous Architecture.
297-304
Electronic Edition (link) BibTeX
- Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima:
High-Speed Logic Simulation on Vector Processors.
305-321
Electronic Edition (link) BibTeX
- Yukihiro Nakamura:
An Integrated Logic Design Environment Based on Behavioral Description.
322-336
Electronic Edition (link) BibTeX
- Takashi Mitsuhashi, Kenji Yoshida:
A Resistance Calculation Algorithm and Its Application to Circuit Extraction.
337-345
Electronic Edition (link) BibTeX
- M. Terai, Y. Ajioka, T. Noda, M. Ozaki, T. Umeki, K. Sato:
Symbolic Layout System: Application Results and Functional Improvements.
346-354
Electronic Edition (link) BibTeX
- Gotaro Odawara, Takahisa Hiraide, Osamu Nishina:
Partitioning and Placement Technique for CMOS Gate Arrays.
355-363
Electronic Edition (link) BibTeX
- Atsushi Kurosawa, Kazutaka Yamada, Aritoyo Kishimoto, Kunio Mori, Nobuyuki Nishiguchi:
A Practical CAD System Application for Full Custom VLSI Microcomputer Chips.
364-373
Electronic Edition (link) BibTeX
- Masaki Ishikawa, T. Matsuda, T. Yoshimura, Satoshi Goto:
Compaction-Based Custom LSI Layout Design Method.
374-382
Electronic Edition (link) BibTeX
- Masahiro Fukui, A. Yamamoto, R. Yamaguchi, Sigeru Hayama, Y. Mano:
A Block Interconnection Algorithm for Hierarchical Layout System.
383-391
Electronic Edition (link) BibTeX
- Takao Nishida, Shunsuke Miyamoto, Tokinori Kozawa, Katsuya Satoh:
RFSIM: Reduced Fault Simulator.
392-402
Electronic Edition (link) BibTeX
- Yoshihiko Hirai, Masaru Sasago, Masayuki Endo, K. Tsuji, Yojiro Mano:
Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process.
403-409
Electronic Edition (link) BibTeX
- S. Isomae, S. Yamamoto:
A New Two-Dimensional Silicon Oxidation Model.
410-416
Electronic Edition (link) BibTeX
- S. Yamamoto, T. Kure, M. Ohgo, Teruo Matsuzawa, S. Tachi, H. Sunami:
A Two-Dimensional Etching Profile Simulator: ESPRIT.
417-422
Electronic Edition (link) BibTeX
- Y. Ohkura, Toru Toyabe, H. Masuda:
Analysis of MOSFET Capacitances and Their Behavior at Short-Channel Lengths Using an AC Device Simulator.
423-430
Electronic Edition (link) BibTeX
- A. Moniwa, Teruo Matsuzawa, T. Ito, H. Sunami:
A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment.
431-438
Electronic Edition (link) BibTeX
- M. Ohgo, Y. Takano, A. Moniwa, S. Yamamoto, Y. Sakai, H. Masuda, H. Sunami:
A Two-Dimensional Integrated Process Simulator: SPIRIT-I.
439-445
Electronic Edition (link) BibTeX
- Teruo Matsuzawa, A. Moniwa, N. Hasegawa, H. Sunami:
Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate.
446-451
Electronic Edition (link) BibTeX
- Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato:
A New Design-Centering Methodology for VLSI Device Development.
452-461
Electronic Edition (link) BibTeX
- Yoichi Shiraishi, Jun'ya Sakemi:
A Permeation Router.
462-471
Electronic Edition (link) BibTeX
- Rakesh Chadha, Kishore Singhal, Jiri Vlach, Ernst Christen, Milan Vlach:
WATOPT -- An Optimizer for Circuit Applications.
472-479
Electronic Edition (link) BibTeX
- Norman P. Jouppi:
Derivation of Signal Flow Direction in MOS VLSI.
480-490
Electronic Edition (link) BibTeX
Volume 6,
Number 4,
July 1987
- Vijay Pitchumani, Qisui Zhang:
A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing.
497-502
Electronic Edition (link) BibTeX
- Majid Sarrafzadeh:
Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete.
503-506
Electronic Edition (link) BibTeX
- A. Margarino, A. Romano, A. De Gloria, Francesco Curatelli, P. Antognetti:
A Tile-Expansion Router.
507-517
Electronic Edition (link) BibTeX
- W. K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong:
A Hierarchical Global Wiring Algorithm for Custom Chip Design.
518-533
Electronic Edition (link) BibTeX
- Saul A. Kravitz, Rob A. Rutenbar:
Placement by Simulated Annealing on a Multiprocessor.
534-549
Electronic Edition (link) BibTeX
- Malgorzata Marek-Sadowska:
Pad Assignment for Power Nets in VLSI Circuits.
550-560
Electronic Edition (link) BibTeX
- Hossein Modarres, Ronald J. Lomax:
A Formal Approach to Design-Rule Checking.
561-573
Electronic Edition (link) BibTeX
- Philip C. Chan, R. Liu, S. K. Lau, Mario Pinto-Guedes:
A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET.
574-581
Electronic Edition (link) BibTeX
- M. C. Hsu, Bing J. Sheu:
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters.
582-585
Electronic Edition (link) BibTeX
- S. L. Wong, C. Andre T. Salama:
Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model.
586-591
Electronic Edition (link) BibTeX
- Ihao Chen, Andrzej J. Strojwas:
A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis.
592-600
Electronic Edition (link) BibTeX
- Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge:
HSS--A High-Speed Simulator.
601-617
Electronic Edition (link) BibTeX
- Randal E. Bryant:
Algorithmic Aspects of Symbolic Switch Network Analysis.
618-633
Electronic Edition (link) BibTeX
- Randal E. Bryant:
Boolean Analysis of MOS Circuits.
634-649
Electronic Edition (link) BibTeX
- Norman P. Jouppi:
Timing Analysis and Performance Improvement of MOS VLSI Designs.
650-665
Electronic Edition (link) BibTeX
- Sumit Ghosh:
A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs.
666-677
Electronic Edition (link) BibTeX
- R. J. Bowman, C. C. Brewster:
Determining the Zeros and Poles of Linear Circuit Networks Using Function Approximation.
678-690
Electronic Edition (link) BibTeX
Volume 6,
Number 5,
September 1987
- Chin Jen Lin, Sudhakar M. Reddy:
On Delay Fault Testing in Logic Circuits.
694-703
Electronic Edition (link) BibTeX
- Kurt Antreich, Michael H. Schulz:
Accelerated Fault Simulation and Fault Grading in Combinational Circuits.
704-712
Electronic Edition (link) BibTeX
- Abhijit Chatterjee, Jacob A. Abraham:
On the C-Testability of Generalized Counters.
713-726
Electronic Edition (link) BibTeX
- Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli:
Multiple-Valued Minimization for PLA Optimization.
727-750
Electronic Edition (link) BibTeX
- Giovanni De Micheli:
Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits.
751-765
Electronic Edition (link) BibTeX
- Douglas S. Reeves, Mary Jane Irwin:
Fast Methods for Switch-Level Verification of MOS Circuits.
766-779
Electronic Edition (link) BibTeX
- Erik C. Carlson, Rob A. Rutenbar:
A Scanline Data Structure Processor for VLSI Geometry Checking.
780-794
Electronic Edition (link) BibTeX
- Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman:
Optimal Chaining of CMOS Transistors in a Functional Cell.
795-801
Electronic Edition (link) BibTeX
- D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang:
An Efficient Approach to Gate Matrix Layout.
802-809
Electronic Edition (link) BibTeX
- K. Winter, Dieter A. Mlynski:
Hierarchical Loose Routing for Gate Arrays.
810-819
Electronic Edition (link) BibTeX
- Gregory B. Sorkin:
Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis.
820-827
Electronic Edition (link) BibTeX
- Wayne Wei-Ming Dai, Ernest S. Kuh:
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout.
828-837
Electronic Edition (link) BibTeX
- Andrea Casotto, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli:
A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells.
838-847
Electronic Edition (link) BibTeX
- William A. Rogers, John F. Guzolek, Jacob A. Abraham:
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
848-862
Electronic Edition (link) BibTeX
- Jürgen Doenhardt, Thomas Lengauer:
Algorithmic Aspects of One-Dimensional Layout Compaction.
863-878
Electronic Edition (link) BibTeX
- Antonio Gnudi, Paolo Ciampolini, Roberto Guerrieri, Massimo Rudan, Giorgio Baccarani:
Sensitivity Analysis for Device Design.
879-885
Electronic Edition (link) BibTeX
- Sung-Mo Kang:
Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout.
886-891
Electronic Edition (link) BibTeX
- Donald L. Dietmeyer:
Local Transformations via Cube Operations.
892-902
Electronic Edition (link) BibTeX
- Jin-fuw Lee, Donald T. Tang:
VLSI Layout Compaction with Grid and Mixed Constraints.
903-910
Electronic Edition (link) BibTeX
Volume 6,
Number 6,
November 1987
- Srinivas Devadas, A. Richard Newton:
Topological Optimization of Multiple-Level Array Logic.
915-941
Electronic Edition (link) BibTeX
- Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli:
A Detailed Router Based on Incremental Routing Modifications: Mighty.
942-955
Electronic Edition (link) BibTeX
- James P. Cohoon, William D. Paris:
Genetic Placement.
956-964
Electronic Edition (link) BibTeX
- Ihao Chen, Andrzej J. Strojwas:
Realistic Yield Simulation for VLSIC Structural Failures.
965-980
Electronic Edition (link) BibTeX
- Robert F. Lucas, Tom Blank, Jerome J. Tiemann:
A Parallel Solution Method for Large Sparse Systems of Equations.
981-991
Electronic Edition (link) BibTeX
- Dundar Dumlugol, Patrick Odent, Johan Cockx, Hugo De Man:
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers.
992-1005
Electronic Edition (link) BibTeX
- Silvano Gai, Fabio Somenzi, Ernst Ulrich:
Advances in Concurrent Multilevel Simulation.
1006-1012
Electronic Edition (link) BibTeX
- Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick:
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI.
1013-1022
Electronic Edition (link) BibTeX
- Joseph E. Hall, Dale E. Hocevar, Ping Yang, Michael J. McGraw:
SPIDER -- A CAD System for Modeling VLSI Metallization Patterns.
1023-1031
Electronic Edition (link) BibTeX
- J. Mar, Krish Bhargavan, Steven G. Duvall, Ram Firestone, Dennis J. Lucey, S. N. Nandgaonkar, S. Wu, Kaung-Shia Yu, F. Zarbakhsh:
EASE--An Application-Based CAD System for Process Design.
1032-1038
Electronic Edition (link) BibTeX
- Jacques Benkoski, Andrzej J. Strojwas:
A New Approach to Hierarchical and Statistical Timing Simulations.
1039-1052
Electronic Edition (link) BibTeX
- Chorng-Yeong Chu, Mark Horowitz:
Charge-Sharing Models for Switch-Level Simulation.
1053-1061
Electronic Edition (link) BibTeX
- Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
MIS: A Multiple-Level Logic Optimization System.
1062-1081
Electronic Edition (link) BibTeX
- Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory:
Testability-Driven Random Test-Pattern Generation.
1082-1087
Electronic Edition (link) BibTeX
- Gabriele Saucier, Michel Crastes de Paulet, Pascal Sicard:
ASYL: A Rule-Based System for Controller Synthesis.
1088-1097
Electronic Edition (link) BibTeX
- Barry M. Pangrle, Daniel D. Gajski:
Design Tools for Intelligent Silicon Compilation.
1098-1112
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:09 2009
by Michael Ley (ley@uni-trier.de)