| 1991 |
|---|
| 4 | EE | Karen A. Bartlett,
Gaetano Borriello,
Sitaram Raju:
Timing optimization of multiphase sequential logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 51-62 (1991) |
| 1988 |
|---|
| 3 | EE | Karen A. Bartlett,
Robert K. Brayton,
Gary D. Hachtel,
Reily M. Jacoby,
Christopher R. Morrison,
Richard L. Rudell,
Alberto L. Sangiovanni-Vincentelli,
Albert R. Wang:
Multi-level logic minimization using implicit don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 723-740 (1988) |
| 1986 |
|---|
| 2 | EE | David Gregory,
Karen A. Bartlett,
Aart J. de Geus,
Gary D. Hachtel:
SOCRATES: a system for automatically synthesizing and optimizing combinational logic.
DAC 1986: 79-85 |
| 1 | EE | Karen A. Bartlett,
William W. Cohen,
Aart J. de Geus,
Gary D. Hachtel:
Synthesis and Optimization of Multilevel Logic under Timing Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 582-596 (1986) |
