VLSI 1991:
Edinburgh,
Scotland
Arne Halaas, Peter B. Denyer (Eds.):
VLSI 91, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991.
IFIP Transactions A-1 North-Holland 1992, ISBN 0-444-89019-X BibTeX
@proceedings{DBLP:conf/vlsi/1991,
editor = {Arne Halaas and
Peter B. Denyer},
title = {VLSI 91, Proceedings of the IFIP TC10/WG 10.5 International Conference
on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August,
1991},
booktitle = {VLSI},
publisher = {North-Holland},
series = {IFIP Transactions},
volume = {A-1},
year = {1992},
isbn = {0-444-89019-X},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1 Arithmetic
Session 2 Digital Signal Processing
Session 3a Formal Methods
Session 3b Physical Design
Session 4a Simulation
Session 4b Vision and Neural Architectures
- Peter B. Denyer, David S. Renshaw, Gouyu Wang, Ming Ying Lu, Stuart Anderson:
On-Chip CMOS Sensors for VLSI Imaging Systems.
157-166 BibTeX
- J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, L. Masse-Navette:
A Customizable Neural Processor for Distributed Neural Network.
167-176 BibTeX
- Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio:
A VLSI Module for Analog Adaptive Neural Architectures.
177-186 BibTeX
Keynote Paper
Session 5 High Level Synthesis
Session 6a Modelling for Synthesis
Session 6b Processor Design
Session 7 RT-Level Synthesis
Session 8a Routing
Session 8b VLSI Arrays
Keynote Paper
- Mitsumasa Koyanagi:
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections.
377-386 BibTeX
Session 9 Circuit Design 1
Session 10 Circuit Design 2
Session 11 Logic Synthesis and Timing Optimisation
Session 12 Fault Tolerant Arrays
Copyright © Sat May 16 23:46:39 2009
by Michael Ley (ley@uni-trier.de)
