| |
| 2008 | ||
|---|---|---|
| 4 | EE | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539 |
| 3 | EE | Aaron P. Hurst: Automatic synthesis of clock gating logic with controlled netlist perturbation. DAC 2008: 654-657 |
| 2007 | ||
| 2 | EE | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187 |
| 2004 | ||
| 1 | EE | Aaron P. Hurst, Philip Chong, Andreas Kuehlmann: Physical placement driven by sequential timing analysis. ICCAD 2004: 379-386 |
| 1 | Robert K. Brayton | [2] [4] |
| 2 | Philip Chong | [1] |
| 3 | Andreas Kuehlmann | [1] |
| 4 | Alan Mishchenko | [2] [4] |