| 2009 |
|---|
| 182 | EE | Rajeev Alur:
Temporal Reasoning about Program Executions.
FOSSACS 2009: 15 |
| 181 | EE | Rajeev Alur,
Aldric Degorre,
Oded Maler,
Gera Weiss:
On Omega-Languages Defined by Mean-Payoff Conditions.
FOSSACS 2009: 333-347 |
| 180 | EE | Gera Weiss,
Sebastian Fischmeister,
Madhukar Anand,
Rajeev Alur:
Specification and Analysis of Network Resource Requirements of Control Systems.
HSCC 2009: 381-395 |
| 2008 |
|---|
| 179 | EE | Rajeev Alur:
Model Checking: From Tools to Theory.
25 Years of Model Checking 2008: 89-106 |
| 178 | EE | Rajeev Alur:
Marrying Words and Trees.
AMAST 2008: 1 |
| 177 | EE | Rajeev Alur,
Aditya Kanade,
Gera Weiss:
Ranking Automata and Games for Prioritized Requirements.
CAV 2008: 240-253 |
| 176 | EE | Rajeev Alur,
Gera Weiss:
RTComposer: a framework for real-time components with scheduling interfaces.
EMSOFT 2008: 159-168 |
| 175 | EE | Rajeev Alur,
Aditya Kanade,
S. Ramesh,
K. C. Shashidhar:
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models.
EMSOFT 2008: 89-98 |
| 174 | EE | Rajeev Alur,
Gera Weiss:
Regular Specifications of Resource Requirements for Embedded Control Software.
IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 159-168 |
| 173 | EE | Rajeev Alur,
Marcelo Arenas,
Pablo Barceló,
Kousha Etessami,
Neil Immerman,
Leonid Libkin:
First-Order and Temporal Logics for Nested Words
CoRR abs/0811.0537: (2008) |
| 172 | EE | Rajeev Alur,
George J. Pappas:
Introduction.
Formal Methods in System Design 32(1): 1 (2008) |
| 171 | EE | Wonhong Nam,
P. Madhusudan,
Rajeev Alur:
Automatic symbolic compositional verification by learning assumptions.
Formal Methods in System Design 32(3): 207-234 (2008) |
| 2007 |
|---|
| 170 | EE | Rajeev Alur:
Marrying Words and Trees.
CSR 2007: 5 |
| 169 | EE | Gera Weiss,
Rajeev Alur:
Automata Based Interfaces for Control and Scheduling.
HSCC 2007: 601-613 |
| 168 | EE | Mikhail Bernadsky,
Rajeev Alur:
Symbolic Analysis for GSMP Models with One Stateful Clock.
HSCC 2007: 90-103 |
| 167 | EE | Rajeev Alur,
Marcelo Arenas,
Pablo Barceló,
Kousha Etessami,
Neil Immerman,
Leonid Libkin:
First-Order and Temporal Logics for Nested Words.
LICS 2007: 151-160 |
| 166 | EE | Sebastian Burckhardt,
Rajeev Alur,
Milo M. K. Martin:
CheckFence: checking consistency of concurrent data types on relaxed memory models.
PLDI 2007: 12-21 |
| 165 | EE | Rajeev Alur:
Marrying words and trees.
PODS 2007: 233-242 |
| 164 | EE | Swarat Chaudhuri,
Rajeev Alur:
Instrumenting C Programs with Nested Word Monitors.
SPIN 2007: 279-283 |
| 163 | EE | Rajeev Alur,
Pavol Cerný,
Swarat Chaudhuri:
Model Checking on Trees with Path Equivalences.
TACAS 2007: 664-678 |
| 162 | EE | Rajeev Alur,
Arun Chandrashekharapuram:
Dispatch sequences for embedded control models.
J. Comput. Syst. Sci. 73(2): 156-170 (2007) |
| 2006 |
|---|
| 161 | EE | Wonhong Nam,
Rajeev Alur:
Learning-Based Symbolic Assume-Guarantee Reasoning with Automatic Decomposition.
ATVA 2006: 170-185 |
| 160 | EE | Rajeev Alur,
Swarat Chaudhuri,
P. Madhusudan:
Languages of Nested Trees.
CAV 2006: 329-342 |
| 159 | EE | Sebastian Burckhardt,
Rajeev Alur,
Milo M. K. Martin:
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study.
CAV 2006: 489-502 |
| 158 | EE | Rajeev Alur,
P. Madhusudan:
Adding Nesting Structure to Words.
Developments in Language Theory 2006: 1-13 |
| 157 | EE | Truong Nghiem,
George J. Pappas,
Rajeev Alur,
Antoine Girard:
Time-triggered implementations of dynamic controllers.
EMSOFT 2006: 2-11 |
| 156 | EE | Rajeev Alur,
Swarat Chaudhuri:
Branching Pushdown Tree Automata.
FSTTCS 2006: 393-404 |
| 155 | EE | Rajeev Alur,
Mikhail Bernadsky:
Bounded Model Checking for GSMP Models of Stochastic Real-Time Systems.
HSCC 2006: 19-33 |
| 154 | EE | Rajeev Alur,
Pavol Cerný,
Steve Zdancewic:
Preserving Secrecy Under Refinement.
ICALP (2) 2006: 107-118 |
| 153 | EE | Rajeev Alur:
Games for formal design and verification of reactive systems.
MEMOCODE 2006: 3 |
| 152 | EE | Rajeev Alur,
Swarat Chaudhuri,
P. Madhusudan:
A fixpoint calculus for local and global program flows.
POPL 2006: 153-165 |
| 151 | EE | Rajeev Alur,
Thao Dang,
Franjo Ivancic:
Predicate abstraction for reachability analysis of hybrid systems.
ACM Trans. Embedded Comput. Syst. 5(1): 152-199 (2006) |
| 150 | EE | Rajeev Alur,
Radu Grosu,
Insup Lee,
Oleg Sokolsky:
Compositional modeling and refinement for hierarchical hybrid systems.
J. Log. Algebr. Program. 68(1-2): 105-128 (2006) |
| 149 | EE | Rajeev Alur,
Salvatore La Torre,
P. Madhusudan:
Modular strategies for recursive game graphs.
Theor. Comput. Sci. 354(2): 230-249 (2006) |
| 148 | EE | Rajeev Alur,
Thao Dang,
Franjo Ivancic:
Counterexample-guided predicate abstraction of hybrid systems.
Theor. Comput. Sci. 354(2): 250-271 (2006) |
| 2005 |
|---|
| 147 | EE | Rajeev Alur,
P. Madhusudan,
Wonhong Nam:
Symbolic Compositional Verification by Learning Assumptions.
CAV 2005: 548-562 |
| 146 | EE | Rajeev Alur:
The Benefits of Exposing Calls and Returns.
CONCUR 2005: 2-3 |
| 145 | EE | Rajeev Alur,
Salvatore La Torre,
P. Madhusudan:
Perturbed Timed Automata.
HSCC 2005: 70-85 |
| 144 | EE | Rajeev Alur,
Viraj Kumar,
P. Madhusudan,
Mahesh Viswanathan:
Congruences for Visibly Pushdown Languages.
ICALP 2005: 1102-1114 |
| 143 | EE | Rajeev Alur,
Arun Chandrashekharapuram:
Dispatch Sequences for Embedded Control Models.
IEEE Real-Time and Embedded Technology and Applications Symposium 2005: 508-518 |
| 142 | EE | Rajeev Alur,
Pavol Cerný,
P. Madhusudan,
Wonhong Nam:
Synthesis of interface specifications for Java classes.
POPL 2005: 98-109 |
| 141 | EE | Hakan Yazarel,
Antoine Girard,
George J. Pappas,
Rajeev Alur:
Quantifying the Gap between Embedded Control Models and Time-Triggered Implementations.
RTSS 2005: 111-120 |
| 140 | EE | Rajeev Alur,
Swarat Chaudhuri,
Kousha Etessami,
P. Madhusudan:
On-the-Fly Reachability and Cycle Detection for Recursive State Machines.
TACAS 2005: 61-76 |
| 139 | EE | Sebastian Burckhardt,
Rajeev Alur,
Milo M. K. Martin:
Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement.
VMCAI 2005: 130-145 |
| 138 | EE | Rajeev Alur:
Trends and Challenges in Algorithmic Software Verification.
VSTTE 2005: 245-250 |
| 137 | EE | Rajeev Alur,
Insup Lee:
Preface.
ACM Trans. Embedded Comput. Syst. 4(4): 707 (2005) |
| 136 | EE | Rajeev Alur,
Michael Benedikt,
Kousha Etessami,
Patrice Godefroid,
Thomas W. Reps,
Mihalis Yannakakis:
Analysis of recursive state machines.
ACM Trans. Program. Lang. Syst. 27(4): 786-818 (2005) |
| 135 | EE | Rajeev Alur,
Kenneth L. McMillan,
Doron Peled:
Deciding Global Partial-Order Properties.
Formal Methods in System Design 26(1): 7-25 (2005) |
| 134 | EE | Rajeev Alur,
P. Madhusudan,
Wonhong Nam:
Symbolic computational techniques for solving games.
STTT 7(2): 118-128 (2005) |
| 133 | EE | Rajeev Alur,
Kousha Etessami,
Mihalis Yannakakis:
Realizability and verification of MSC graphs.
Theor. Comput. Sci. 331(1): 97-114 (2005) |
| 2004 |
|---|
| 132 | | Rajeev Alur,
George J. Pappas:
Hybrid Systems: Computation and Control, 7th International Workshop, HSCC 2004, Philadelphia, PA, USA, March 25-27, 2004, Proceedings
Springer 2004 |
| 131 | | Rajeev Alur,
Doron Peled:
Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings
Springer 2004 |
| 130 | EE | Rajeev Alur:
Games for Formal Design and Verification of Reactive Systems.
ATVA 2004: 1 |
| 129 | EE | Michael McDougall,
Rajeev Alur,
Carl A. Gunter:
A model-based approach to integrating security policies for embedded devices.
EMSOFT 2004: 211-219 |
| 128 | EE | Zijiang Yang,
Rajeev Alur:
Variable Reuse for Efficient Image Computation.
FMCAD 2004: 430-444 |
| 127 | EE | Mikhail Bernadsky,
Raman Sharykin,
Rajeev Alur:
Structured Modeling of Concurrent Stochastic Hybrid Systems.
FORMATS/FTRTFT 2004: 309-324 |
| 126 | EE | Rajeev Alur,
Mikhail Bernadsky,
P. Madhusudan:
Optimal Reachability for Weighted Timed Games.
ICALP 2004: 122-133 |
| 125 | EE | Rajeev Alur,
P. Madhusudan:
Decision Problems for Timed Automata: A Survey.
SFM 2004: 1-24 |
| 124 | EE | Rajeev Alur,
P. Madhusudan:
Visibly pushdown languages.
STOC 2004: 202-211 |
| 123 | EE | Rajeev Alur,
Kousha Etessami,
P. Madhusudan:
A Temporal Logic of Nested Calls and Returns.
TACAS 2004: 467-481 |
| 122 | EE | Rajeev Alur,
Salvatore La Torre:
Deterministic generators and games for Ltl fragments.
ACM Trans. Comput. Log. 5(1): 1-25 (2004) |
| 121 | EE | Rajeev Alur,
Radu Grosu:
Modular refinement of hierarchic reactive machines.
ACM Trans. Program. Lang. Syst. 26(2): 339-369 (2004) |
| 120 | EE | Rajeev Alur,
Sampath Kannan,
Salvatore La Torre:
Polyhedral Flows in Hybrid Automata.
Formal Methods in System Design 24(3): 261-280 (2004) |
| 119 | EE | Rajeev Alur,
David Arney,
Elsa L. Gunter,
Insup Lee,
Jaime Lee,
Wonhong Nam,
Frederick Pearce,
Stephen Van Albert,
Jiaxiang Zhou:
Formal specifications and analysis of the computer-assisted resuscitation algorithm (CARA) Infusion Pump Control System.
STTT 5(4): 308-319 (2004) |
| 118 | EE | Rajeev Alur,
Salvatore La Torre,
George J. Pappas:
Optimal paths in weighted timed automata.
Theor. Comput. Sci. 318(3): 297-322 (2004) |
| 2003 |
|---|
| 117 | | Rajeev Alur,
Insup Lee:
Embedded Software, Third International Conference, EMSOFT 2003, Philadelphia, PA, USA, October 13-15, 2003, Proceedings
Springer 2003 |
| 116 | EE | Rajeev Alur,
Salvatore La Torre,
P. Madhusudan:
Modular Strategies for Infinite Games on Recursive Graphs.
CAV 2003: 67-79 |
| 115 | EE | Rajeev Alur,
Salvatore La Torre,
P. Madhusudan:
Playing Games with Boxes and Diamonds.
CONCUR 2003: 127-141 |
| 114 | EE | Rajeev Alur,
Swarat Chaudhuri,
Kousha Etessami,
Sudipto Guha,
Mihalis Yannakakis:
Compression of Partially Ordered Strings.
CONCUR 2003: 42-56 |
| 113 | EE | Rajeev Alur,
Thao Dang,
Franjo Ivancic:
Progress on Reachability Analysis of Hybrid Systems Using Predicate Abstraction.
HSCC 2003: 4-19 |
| 112 | EE | Rajeev Alur,
Franjo Ivancic,
Jesung Kim,
Insup Lee,
Oleg Sokolsky:
Generating embedded software from hierarchical hybrid models.
LCTES 2003: 171-182 |
| 111 | EE | Rajeev Alur,
Thao Dang,
Franjo Ivancic:
Counter-Example Guided Predicate Abstraction of Hybrid Systems.
TACAS 2003: 208-223 |
| 110 | EE | Rajeev Alur,
Salvatore La Torre,
P. Madhusudan:
Modular Strategies for Recursive Game Graphs.
TACAS 2003: 363-378 |
| 109 | EE | Rajeev Alur:
Formal Analysis of Hierarchical State Machines.
Verification: Theory and Practice 2003: 42-66 |
| 108 | EE | P. Madhusudan,
Wonhong Nam,
Rajeev Alur:
Symbolic computational techniques for solving games.
Electr. Notes Theor. Comput. Sci. 89(4): (2003) |
| 107 | EE | Rajeev Alur,
Kousha Etessami,
Mihalis Yannakakis:
Inference of Message Sequence Charts.
IEEE Trans. Software Eng. 29(7): 623-633 (2003) |
| 106 | | Rajeev Alur,
Thao Dang,
Joel M. Esposito,
Yerang Hur,
Franjo Ivancic,
Vijay Kumar,
Insup Lee,
Pradyumna Mishra,
George J. Pappas,
Oleg Sokolsky:
Hierarchical modeling and analysis of embedded systems.
Proceedings of the IEEE 91(1): 11-28 (2003) |
| 2002 |
|---|
| 105 | EE | Alwyn Goodloe,
Michael McDougall,
Carl A. Gunter,
Rajeev Alur:
Predictable programs in barcodes.
CASES 2002: 298-303 |
| 104 | EE | Rajeev Alur,
Michael McDougall,
Zijiang Yang:
Exploiting Behavioral Hierarchy for Efficient Model Checking.
CAV 2002: 338-342 |
| 103 | EE | Rajeev Alur,
Thao Dang,
Franjo Ivancic:
Reachability Analysis of Hybrid Systems via Predicate Abstraction.
HSCC 2002: 35-48 |
| 102 | EE | Rajeev Alur,
Calin Belta,
Franjo Ivancic,
Vijay Kumar,
Harvey Rubin,
Jonathan Schug,
Oleg Sokolsky,
Jonathan Webb:
Visual Programming for Modeling and Simulation of Biomolecular Regulatory Networks.
HiPC 2002: 702-712 |
| 101 | | Rafael B. Fierro,
Aveek K. Das,
John R. Spletzer,
Joel M. Esposito,
Vijay Kumar,
James P. Ostrowski,
George J. Pappas,
Camillo J. Taylor,
Yerang Hur,
Rajeev Alur,
Insup Lee,
Gregory Z. Grudic,
Ben Southall:
A Framework and Architecture for Multi-Robot Coordination.
I. J. Robotic Res. 21(10-11): 977-998 (2002) |
| 100 | EE | Rajeev Alur,
Thomas A. Henzinger,
Orna Kupferman:
Alternating-time temporal logic.
J. ACM 49(5): 672-713 (2002) |
| 2001 |
|---|
| 99 | EE | Rajeev Alur,
Radu Grosu:
Shared Variables Interaction Diagrams.
ASE 2001: 281-288 |
| 98 | EE | Rajeev Alur,
Bow-Yaw Wang:
Verifying Network Protocol Implementations by Symbolic Refinement Checking.
CAV 2001: 169-181 |
| 97 | EE | Rajeev Alur,
Kousha Etessami,
Mihalis Yannakakis:
Analysis of Recursive State Machines.
CAV 2001: 207-220 |
| 96 | EE | M. Oliver Möller,
Rajeev Alur:
Heuristics for Hierarchical Partitioning with Application to Model Checking.
CHARME 2001: 71-85 |
| 95 | EE | Rajeev Alur,
Thao Dang,
Joel M. Esposito,
Rafael B. Fierro,
Yerang Hur,
Franjo Ivancic,
Vijay Kumar,
Insup Lee,
Pradyumna Mishra,
George J. Pappas,
Oleg Sokolsky:
Hierarchical Hybrid Modeling of Embedded Systems.
EMSOFT 2001: 14-31 |
| 94 | EE | Rajeev Alur,
Calin Belta,
Franjo Ivancic:
Hybrid Modeling and Simulation of Biomolecular Networks.
HSCC 2001: 19-32 |
| 93 | EE | Rajeev Alur,
Radu Grosu,
Insup Lee,
Oleg Sokolsky:
Compositional Refinement for Hierarchical Hybrid Systems.
HSCC 2001: 33-48 |
| 92 | EE | Rajeev Alur,
Salvatore La Torre,
George J. Pappas:
Optimal Paths in Weighted Timed Automata.
HSCC 2001: 49-62 |
| 91 | EE | Rajeev Alur,
Kousha Etessami,
Mihalis Yannakakis:
Realizability and Verification of MSC Graphs.
ICALP 2001: 797-808 |
| 90 | | Rajeev Alur,
Luca de Alfaro,
Radu Grosu,
Thomas A. Henzinger,
M. Kang,
Christoph M. Kirsch,
Rupak Majumdar,
Freddy Y. C. Mang,
Bow-Yaw Wang:
JMOCHA: A Model Checking Tool that Exploits Design Structure.
ICSE 2001: 835-836 |
| 89 | | Rajeev Alur,
Salvatore La Torre:
Deterministic Generators and Games for LTL Fragments.
LICS 2001: 291-302 |
| 88 | EE | Rajeev Alur,
Kousha Etessami,
Salvatore La Torre,
Doron Peled:
Parametric temporal logic for "model measuring".
ACM Trans. Comput. Log. 2(3): 388-407 (2001) |
| 87 | EE | Rajeev Alur,
Mihalis Yannakakis:
Model checking of hierarchical state machines.
ACM Trans. Program. Lang. Syst. 23(3): 273-303 (2001) |
| 86 | | Rajeev Alur,
Robert K. Brayton,
Thomas A. Henzinger,
Shaz Qadeer,
Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State-Space Exploration.
Formal Methods in System Design 18(2): 97-116 (2001) |
| 85 | | Rajeev Alur,
Thomas A. Henzinger:
Introduction.
Inf. Comput. 164(2): 233 (2001) |
| 2000 |
|---|
| 84 | | Rajeev Alur,
Radu Grosu,
Michael McDougall:
Efficient Reachability Analysis of Hierarchical Reactive Machines.
CAV 2000: 280-295 |
| 83 | EE | Rajeev Alur:
Exploiting Hierarchical Structure for Efficient Formal Verification.
CONCUR 2000: 66-68 |
| 82 | EE | Rajeev Alur,
Radu Grosu,
Bow-Yaw Wang:
Automated Refinement Checking for Asynchronous Processes.
FMCAD 2000: 55-72 |
| 81 | EE | Rajeev Alur,
Radu Grosu,
Yerang Hur,
Vijay Kumar,
Insup Lee:
Modular Specification of Hybrid Systems in CHARON.
HSCC 2000: 6-19 |
| 80 | EE | Rajeev Alur,
Kousha Etessami,
Mihalis Yannakakis:
Inference of message sequence charts.
ICSE 2000: 304-313 |
| 79 | EE | Rajeev Alur,
Aveek K. Das,
Joel M. Esposito,
Rafael B. Fierro,
Gregory Z. Grudic,
Yerang Hur,
Vijay Kumar,
Insup Lee,
J. P. Lee,
James P. Ostrowski,
George J. Pappas,
Ben Southall,
John R. Spletzer,
Camillo J. Taylor:
A Framework and Architecture for Multirobot Coordination.
ISER 2000: 303-312 |
| 78 | EE | Rajeev Alur,
Radu Grosu:
Modular Refinement of Hierarchic Reactive Machines.
POPL 2000: 390-402 |
| 77 | | Rajeev Alur,
Kenneth L. McMillan,
Doron Peled:
Model-Checking of Correctness Conditions for Concurrent Objects.
Inf. Comput. 160(1-2): 167-188 (2000) |
| 1999 |
|---|
| 76 | EE | Rajeev Alur:
Timed Automata.
CAV 1999: 8-22 |
| 75 | EE | Rajeev Alur,
Mihalis Yannakakis:
Model Checking of Message Sequence Charts.
CONCUR 1999: 114-129 |
| 74 | EE | Rajeev Alur,
Luca de Alfaro,
Thomas A. Henzinger,
Freddy Y. C. Mang:
Automating Modular Verification.
CONCUR 1999: 82-97 |
| 73 | EE | Rajeev Alur,
Bow-Yaw Wang:
``Next'' Heuristic for On-the-Fly Model Checking.
CONCUR 1999: 98-113 |
| 72 | EE | Rajeev Alur,
Sampath Kannan,
Salvatore La Torre:
Polyhedral Flows in Hybrid Automata.
HSCC 1999: 5-18 |
| 71 | EE | Rajeev Alur,
Kousha Etessami,
Salvatore La Torre,
Doron Peled:
Parametric Temporal Logic for "Model Measuring".
ICALP 1999: 159-168 |
| 70 | EE | Rajeev Alur,
Sampath Kannan,
Mihalis Yannakakis:
Communicating Hierarchical State Machines.
ICALP 1999: 169-178 |
| 69 | EE | Rajeev Alur,
Joel M. Esposito,
M. Kim,
Vijay Kumar,
Insup Lee:
Formal Modeling and Analysis of Hybrid Systems: A Case Study in Multi-robot Coordination.
World Congress on Formal Methods 1999: 212-232 |
| 68 | | Rajeev Alur,
Thomas A. Henzinger:
Introduction.
Formal Methods in System Design 14(3): 235 (1999) |
| 67 | | Rajeev Alur,
Thomas A. Henzinger:
Introduction.
Formal Methods in System Design 15(1): 5 (1999) |
| 66 | | Rajeev Alur,
Thomas A. Henzinger:
Reactive Modules.
Formal Methods in System Design 15(1): 7-48 (1999) |
| 65 | EE | Rajeev Alur,
Doron Peled:
Undecidability of Partial Order Logics.
Inf. Process. Lett. 69(3): 137-143 (1999) |
| 64 | EE | Rajeev Alur,
Limor Fix,
Thomas A. Henzinger:
Event-Clock Automata: A Determinizable Class of Timed Automata.
Theor. Comput. Sci. 211(1-2): 253-273 (1999) |
| 1998 |
|---|
| 63 | | Rajeev Alur,
Thomas A. Henzinger,
Freddy Y. C. Mang,
Shaz Qadeer,
Sriram K. Rajamani,
Serdar Tasiran:
MOCHA: Modularity in Model Checking.
CAV 1998: 521-525 |
| 62 | EE | Rajeev Alur,
Thomas A. Henzinger,
Orna Kupferman,
Moshe Y. Vardi:
Alternating Refinement Relations.
CONCUR 1998: 163-178 |
| 61 | EE | Allen D. Malony,
Rajeev Alur:
Performance Evaluation and Prediction.
Euro-Par 1998: 191-192 |
| 60 | | Rajeev Alur:
Efficient Formal Verification of Hierarchical Descriptions.
FSTTCS 1998: 269 |
| 59 | EE | Rajeev Alur,
Kenneth L. McMillan,
Doron Peled:
Deciding Global Partial-Order Properties.
ICALP 1998: 41-52 |
| 58 | EE | Rajeev Alur,
Robert P. Kurshan,
Mahesh Viswanathan:
Membership Questions for Timed and Hybrid Automata.
IEEE Real-Time Systems Symposium 1998: 254-263 |
| 57 | EE | Rajeev Alur,
Mihalis Yannakakis:
Model Checking of Hierarchical State Machines.
SIGSOFT FSE 1998: 175-188 |
| 56 | EE | Rajeev Alur,
Thomas A. Henzinger,
Sriram K. Rajamani:
Symbolic Exploration of transition Hierarchies.
TACAS 1998: 330-344 |
| 55 | EE | Rajeev Alur,
Thomas A. Henzinger:
Finitary Fairness.
ACM Trans. Program. Lang. Syst. 20(6): 1171-1194 (1998) |
| 1997 |
|---|
| 54 | | Rajeev Alur,
Robert K. Brayton,
Thomas A. Henzinger,
Shaz Qadeer,
Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State Space Exploration.
CAV 1997: 340-351 |
| 53 | EE | Rajeev Alur,
Thomas A. Henzinger,
Orna Kupferman:
Alternating-Time Temporal Logic.
COMPOS 1997: 23-60 |
| 52 | | Rajeev Alur,
Thomas A. Henzinger:
Modularity for Timed and Hybrid Systems.
CONCUR 1997: 74-88 |
| 51 | EE | Rajeev Alur,
Thomas A. Henzinger,
Orna Kupferman:
Alternating-time Temporal Logic.
FOCS 1997: 100-109 |
| 50 | EE | Rajeev Alur,
Lalita Jategaonkar Jagadeesan,
Joseph J. Kott,
James Von Olnhausen:
Model-Checking of Real-Time Systems: A Telecommunications Application (Experience Report).
ICSE 1997: 514-524 |
| 49 | | Rajeev Alur,
Costas Courcoubetis,
Thomas A. Henzinger:
Computing Accumulated Delays in Real-time Systems.
Formal Methods in System Design 11(2): 137-155 (1997) |
| 48 | | Rajeev Alur,
Hagit Attiya,
Gadi Taubenfeld:
Time-Adaptive Algorithms for Synchronization.
SIAM J. Comput. 26(2): 539-556 (1997) |
| 47 | EE | Rajeev Alur,
Thomas A. Henzinger:
Real-Time System = Discrete System + Clock Variables.
STTT 1(1-2): 86-109 (1997) |
| 1996 |
|---|
| 46 | | Rajeev Alur,
Thomas A. Henzinger,
Eduardo D. Sontag:
Hybrid Systems III: Verification and Control, Proceedings of the DIMACS/SYCON Workshop, October 22-25, 1995, Ruttgers University, New Brunswick, NJ, USA
Springer 1996 |
| 45 | | Rajeev Alur,
Thomas A. Henzinger:
Computer Aided Verification, 8th International Conference, CAV '96, New Brunswick, NJ, USA, July 31 - August 3, 1996, Proceedings
Springer 1996 |
| 44 | | Serdar Tasiran,
Rajeev Alur,
Robert P. Kurshan,
Robert K. Brayton:
Verifying Abstractions of Timed Systems.
CONCUR 1996: 546-562 |
| 43 | | Rajeev Alur,
Thomas A. Henzinger:
Reactive Modules.
LICS 1996: 207-218 |
| 42 | | Rajeev Alur,
Kenneth L. McMillan,
Doron Peled:
Model-Checking of Correctness Conditions for Concurrent Objects.
LICS 1996: 219-228 |
| 41 | | Rajeev Alur,
Gerard J. Holzmann,
Doron Peled:
An Analyser for Mesage Sequence Charts.
TACAS 1996: 35-48 |
| 40 | | Rajeev Alur:
Next Steps in Formal Verification.
ACM Comput. Surv. 28(4es): 115 (1996) |
| 39 | | Rajeev Alur,
Gadi Taubenfeld:
Fast Timing-Based Algorithms.
Distributed Computing 10(1): 1-10 (1996) |
| 38 | EE | Rajeev Alur,
Thomas A. Henzinger,
Pei-Hsin Ho:
Automatic Symbolic Verification of Embedded Systems.
IEEE Trans. Software Eng. 22(3): 181-201 (1996) |
| 37 | | Rajeev Alur,
Gadi Taubenfeld:
Contention-Free Complexity of Shared Memory Algorithms.
Inf. Comput. 126(1): 62-73 (1996) |
| 36 | EE | Rajeev Alur,
Tomás Feder,
Thomas A. Henzinger:
The Benefits of Relaxing Punctuality.
J. ACM 43(1): 116-146 (1996) |
| 35 | | Rajeev Alur,
Gerard J. Holzmann,
Doron Peled:
An Analyzer for Message Sequence Charts.
Software - Concepts and Tools 17(2): 70-77 (1996) |
| 1995 |
|---|
| 34 | | Rajeev Alur,
Thomas A. Henzinger:
Local Liveness for Compositional Modeling of Fair Reactive Systems.
CAV 1995: 166-179 |
| 33 | | Rajeev Alur,
Robert P. Kurshan:
Timing Analysis in COSPAN.
Hybrid Systems 1995: 220-231 |
| 32 | | Rajeev Alur,
Doron Peled,
Wojciech Penczek:
Model-Checking of Causality Properties
LICS 1995: 90-100 |
| 31 | EE | Rajeev Alur,
Costas Courcoubetis,
Mihalis Yannakakis:
Distinguishing tests for nondeterministic and probabilistic machines.
STOC 1995: 363-372 |
| 30 | | Rajeev Alur,
Alon Itai,
Robert P. Kurshan,
Mihalis Yannakakis:
Timing Verification by Successive Approximation
Inf. Comput. 118(1): 142-157 (1995) |
| 29 | EE | Rajeev Alur,
Costas Courcoubetis,
Nicolas Halbwachs,
Thomas A. Henzinger,
Pei-Hsin Ho,
Xavier Nicollin,
Alfredo Olivero,
Joseph Sifakis,
Sergio Yovine:
The Algorithmic Analysis of Hybrid Systems.
Theor. Comput. Sci. 138(1): 3-34 (1995) |
| 1994 |
|---|
| 28 | | Rajeev Alur,
Limor Fix,
Thomas A. Henzinger:
A Determinizable Class of Timed Automata.
CAV 1994: 1-13 |
| 27 | | Rajeev Alur,
Costas Courcoubetis,
Thomas A. Henzinger:
The Observational Power of Clocks.
CONCUR 1994: 162-177 |
| 26 | | Rajeev Alur,
Thomas A. Henzinger:
Finitary Fairness
LICS 1994: 52-61 |
| 25 | | Rajeev Alur,
Gadi Taubenfeld:
Contention-free Complexity of Shared Memory Algorithms.
PODC 1994: 61-70 |
| 24 | EE | Rajeev Alur,
Hagit Attiya,
Gadi Taubenfeld:
Time-adaptive algorithms for synchronization.
STOC 1994: 800-809 |
| 23 | EE | Rajeev Alur,
Thomas A. Henzinger:
A Really Temporal Logic.
J. ACM 41(1): 181-204 (1994) |
| 22 | | Rajeev Alur,
David L. Dill:
A Theory of Timed Automata.
Theor. Comput. Sci. 126(2): 183-235 (1994) |
| 1993 |
|---|
| 21 | | Rajeev Alur,
Costas Courcoubetis,
Thomas A. Henzinger:
Computing Accumulated Delays in Real-time Systems.
CAV 1993: 181-193 |
| 20 | | Rajeev Alur,
Thomas A. Henzinger,
Pei-Hsin Ho:
Automatic Symbolic Verification of Embedded Systems.
IEEE Real-Time Systems Symposium 1993: 2-11 |
| 19 | | Rajeev Alur,
Gadi Taubenfeld:
How to Share an Object: A Fast Timing-Based Solution.
SPDP 1993: 470-477 |
| 18 | EE | Rajeev Alur,
Thomas A. Henzinger,
Moshe Y. Vardi:
Parametric real-time reasoning.
STOC 1993: 592-601 |
| 17 | | Rajeev Alur,
Costas Courcoubetis,
David L. Dill:
Model-Checking in Dense Real-time
Inf. Comput. 104(1): 2-34 (1993) |
| 16 | | Rajeev Alur,
Thomas A. Henzinger:
Real-Time Logics: Complexity and Expressiveness
Inf. Comput. 104(1): 35-77 (1993) |
| 1992 |
|---|
| 15 | | Rajeev Alur,
Alon Itai,
Robert P. Kurshan,
Mihalis Yannakakis:
Timing Verification by Successive Approximation.
CAV 1992: 137-150 |
| 14 | | Rajeev Alur,
Costas Courcoubetis,
Nicolas Halbwachs,
David L. Dill,
Howard Wong-Toi:
Minimization of Timed Transition Systems.
CONCUR 1992: 340-354 |
| 13 | | Rajeev Alur,
Thomas A. Henzinger:
Back to the Future: Towards a Theory of Timed Regular Languages
FOCS 1992: 177-186 |
| 12 | | Rajeev Alur,
Costas Courcoubetis,
Thomas A. Henzinger,
Pei-Hsin Ho:
Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems.
Hybrid Systems 1992: 209-229 |
| 11 | EE | Rajeev Alur,
Gadi Taubenfeld:
Results about Fast Mutual Exclusion.
IEEE Real-Time Systems Symposium 1992: 12-22 |
| 10 | EE | Rajeev Alur,
Costas Courcoubetis,
David L. Dill,
Nicolas Halbwachs,
Howard Wong-Toi:
An implementation of three algorithms for timing verification based on automata emptiness.
IEEE Real-Time Systems Symposium 1992: 157-166 |
| 1991 |
|---|
| 9 | | Rajeev Alur,
Costas Courcoubetis,
David L. Dill:
Model-Checking for Probabilistic Real-Time Systems (Extended Abstract).
ICALP 1991: 115-126 |
| 8 | | Rajeev Alur,
Tomás Feder,
Thomas A. Henzinger:
The Benefits of Relaxing Punctuality.
PODC 1991: 139-152 |
| 7 | | Rajeev Alur,
Costas Courcoubetis,
David L. Dill:
Verifying Automata Specifications of Probabilistic Real-time Systems.
REX Workshop 1991: 28-44 |
| 6 | | Rajeev Alur,
David L. Dill:
The Theory of Timed Automata.
REX Workshop 1991: 45-73 |
| 5 | | Rajeev Alur,
Thomas A. Henzinger:
Logics and Models of Real Time: A Survey.
REX Workshop 1991: 74-106 |
| 1990 |
|---|
| 4 | | Rajeev Alur,
David L. Dill:
Automata For Modeling Real-Time Systems.
ICALP 1990: 322-335 |
| 3 | | Rajeev Alur,
Thomas A. Henzinger:
Real-time Logics: Complexity and Expressiveness
LICS 1990: 390-401 |
| 2 | | Rajeev Alur,
Costas Courcoubetis,
David L. Dill:
Model-Checking for Real-Time Systems
LICS 1990: 414-425 |
| 1989 |
|---|
| 1 | | Rajeev Alur,
Thomas A. Henzinger:
A Really Temporal Logic
FOCS 1989: 164-169 |
