The Journal of VLSI Signal Processing, Volume 7

Volume 7, Numbers 1-2, February 1994

• Teresa H. Y. Meng, Sharad Malik:
  Editorial. 5-6
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• Mark E. Dean, David L. Dill, Mark Horowitz:
  Self-timed logic using Current-Sensing Completion Detection (CSCD). 7-16
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• Ted E. Williams:
  Performance of iterative computation in self-timed rings. 17-31
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• Ganesh Gopalakrishnan, Venkatesh Akella:
  High-level optimizations in compiling process descriptions to asynchronous circuits. 33-45
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• Erik Brunvand:
  Designing self-timed systems using concurrent programs. 47-59
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• Tam-Anh Chu:
  Synthesis of hazard-free control circuits from asynchronous finite state machines specifications. 61-84
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• Cho W. Moon, Paul R. Stephan, Robert K. Brayton:
  Specification, synthesis, and verification of hazard-free asynchronous circuits. 85-100
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• Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man:
  A generalized state assignment theory for transformations on signal transition graphs. 101-115
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• Michael Kishinevsky, Alex Kondratyev, Alexander Taubin:
  Specification and analysis of self-timed circuits. 117-135
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• Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli:
  Linear programming for hazard elimination in asynchronous circuits. 137-160
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• Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang:
  Verification of asynchronous interface circuits with bounded wire delays. 161-182
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Volume 7, Number 3, October 1994

• John S. Fernando, Milos D. Ercegovac:
  Conventional and on-line arithmetic designs for high-speed recursive digital filters. 189-197
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• Poornachandra B. Rao, Alexander Skavantzos:
  ROM based methods for computing the squaring operation in modular rings. 199-211
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• Vojin G. Oklobdzija, David Villeger, Thierry Soulas:
  An integrated multiplier for complex numbers. 213-222
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• Robert F. Jones, Earl E. Swartzlander Jr.:
  Parallel counter implementation. 223-232
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• Fabian Klass, Michael J. Flynn, A. J. van de Goor:
  Fast multiplication in VLSI using wave pipelining techniques. 233-248
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• Ben C. Drerup, Earl E. Swartzlander Jr.:
  Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. 249-257
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• Paolo Montuschi, Luigi Ciminiera:
  Radix-8 division with over-redundant digit set. 259-270
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• Marianne E. Louie, Milos D. Ercegovac:
  Implementing division with field programmable gate arrays. 271-285
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