| 2007 |
|---|
| 6 | EE | Ilhan Hatirnaz,
Stéphane Badel,
Nuria Pazos,
Yusuf Leblebici,
Srinivasan Murali,
David Atienza,
Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects.
SLIP 2007: 57-64 |
| 2006 |
|---|
| 5 | EE | Derin Derin Harmanci,
Nuria Pazos,
Paolo Ienne,
Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems.
VLSI-SoC 2006: 152-157 |
| 2003 |
|---|
| 4 | EE | Winthir Brunnbauer,
Thomas Wild,
Jürgen Foag,
Nuria Pazos:
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges.
DSD 2003: 98-103 |
| 3 | EE | Thomas Wild,
Jürgen Foag,
Nuria Pazos,
Winthir Brunnbauer:
Mapping and Scheduling for Architecture Exploration of Networking SoCs.
VLSI Design 2003: 376-381 |
| 2002 |
|---|
| 2 | EE | Jürgen Foag,
Nuria Pazos,
Thomas Wild,
Winthir Brunnbauer:
Self-Adaptive Parallel Processing Architecture For High-speed Networking.
HPCS 2002: 45-52 |
| 1 | EE | Jürgen Foag,
Thomas Wild,
Nuria Pazos,
Winthir Brunnbauer:
Predictive methodology for high-performance networking.
ISCC 2002: 169-174 |
