2009 |
31 | EE | Maurizio Palesi,
Rickard Holsmark,
Shashi Kumar,
Vincenzo Catania:
Application Specific Routing Algorithms for Networks on Chip.
IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009) |
2008 |
30 | EE | Maurizio Palesi,
Giuseppe Longo,
Salvatore Signorino,
Rickard Holsmark,
Shashi Kumar,
Vincenzo Catania:
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.
NOCS 2008: 97-106 |
29 | EE | Rickard Holsmark,
Maurizio Palesi,
Shashi Kumar:
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions.
Journal of Systems Architecture - Embedded Systems Design 54(3-4): 427-440 (2008) |
2007 |
28 | EE | Maurizio Palesi,
Shashi Kumar,
Rickard Holsmark,
Vincenzo Catania:
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.
IPDPS 2007: 1-8 |
27 | EE | Shashi Kumar,
Sanjeev Kumar,
Prakash,
Ravi Shankar,
M. K. Tiwari,
Shashi Bhushan Kumar:
Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks.
Expert Syst. Appl. 32(3): 777-788 (2007) |
26 | EE | Rickard Holsmark,
Shashi Kumar:
Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks.
J. Inf. Sci. Eng. 23(6): 1649-1662 (2007) |
2006 |
25 | EE | Maurizio Palesi,
Rickard Holsmark,
Shashi Kumar,
Vincenzo Catania:
A methodology for design of application specific deadlock-free routing algorithms for NoC systems.
CODES+ISSS 2006: 142-147 |
24 | EE | Tomas Bengtsson,
Artur Jutman,
Shashi Kumar,
Raimund Ubar,
Zebo Peng:
Off-Line Testing of Delay Faults in NoC Interconnects.
DSD 2006: 677-680 |
23 | EE | Rickard Holsmark,
Maurizio Palesi,
Shashi Kumar:
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.
DSD 2006: 696-703 |
22 | EE | Maurizio Palesi,
Shashi Kumar,
Rickard Holsmark:
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.
SAMOS 2006: 373-384 |
2005 |
21 | EE | Daniel Andreasson,
Shashi Kumar:
Slack-time aware routing in NoC systems.
ISCAS (3) 2005: 2353-2356 |
2004 |
20 | EE | Mikael Millberg,
Erland Nilsson,
Rikard Thid,
Shashi Kumar,
Axel Jantsch:
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.
VLSI Design 2004: 693-696 |
2003 |
19 | EE | Tang Lei,
Shashi Kumar:
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture.
DSD 2003: 180-189 |
18 | EE | Tang Lei,
Shashi Kumar:
Algorithms and Tools for Network on Chip Based System Design.
SBCCI 2003: 163-168 |
17 | EE | Rickard Holsmark,
Magnus Högberg,
Shashi Kumar:
Modelling and Evaluation of a Network on Chip Architecture Using SDL.
SDL Forum 2003: 166-182 |
16 | EE | Juha-Pekka Soininen,
Axel Jantsch,
Martti Forsell,
Antti Pelkonen,
Jari Kreku,
Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems.
VLSI Design 2003: 401- |
2002 |
15 | EE | Sushil Chandra Jain,
Anshul Kumar,
Shashi Kumar:
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.
IEEE International Workshop on Rapid System Prototyping 2002: 66- |
14 | EE | Shashi Kumar,
Axel Jantsch,
Mikael Millberg,
Johnny Öberg,
Juha-Pekka Soininen,
Martti Forsell,
Kari Tiensyrjä,
Ahmed Hemani:
A Network on Chip Architecture and Design Methodology.
ISVLSI 2002: 117-124 |
2000 |
13 | EE | Sushil Chandra Jain,
Anshul Kumar,
Shashi Kumar:
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
FPL 2000: 201-210 |
12 | EE | Aviral Shrivastava,
Mohit Kumar,
Sanjiv Kapoor,
Shashi Kumar,
M. Balakrishnan:
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
VLSI Design 2000: 110-113 |
11 | EE | Sushil Chandra Jain,
Shashi Kumar,
Anshul Kumar:
Evaluation of Various Routing Architectures for Multi-FPGA Boards.
VLSI Design 2000: 262-267 |
10 | EE | Axel Jantsch,
Shashi Kumar,
Ahmed Hemani:
A Metamodel for Studying Concepts in Electronic System Design.
IEEE Design & Test of Computers 17(3): 78-85 (2000) |
1999 |
9 | EE | Ahmed Hemani,
Thomas Meincke,
Shashi Kumar,
Adam Postula,
Thomas Olsson,
Peter Nilsson,
Johnny Öberg,
Peeter Ellervee,
Dan Lundqvist:
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.
DAC 1999: 873-878 |
8 | EE | Axel Jantsch,
Shashi Kumar,
Ahmed Hemani:
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.
DATE 1999: 256-262 |
7 | EE | Thomas Meincke,
Ahmed Hemani,
Shashi Kumar,
Peeter Ellervee,
Johnny Öberg,
Thomas Olsson,
Peter Nilsson,
Dan Lindqvist,
Hannu Tenhunen:
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
ISCAS (2) 1999: 512-515 |
1998 |
6 | | Sitanshu Jain,
M. Balakrishnan,
Anshul Kumar,
Shashi Kumar:
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
VLSI Design 1998: 400-405 |
5 | | Bengt Svantesson,
Shashi Kumar,
Ahmed Hemani:
A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL.
VLSI Design 1998: 78-84 |
1997 |
4 | EE | Gaurav Aggarwal,
Nitin Thaper,
Kamal Aggarwal,
M. Balakrishnan,
Shashi Kumar:
A Novel Reconfigurable Co-Processor Architecture.
VLSI Design 1997: 370-375 |
1996 |
3 | EE | S. Harikumar,
Shashi Kumar:
Iterative Deepening Multiobjective A.
Inf. Process. Lett. 58(1): 11-15 (1996) |
1995 |
2 | EE | B. M. Subraya,
Anshul Kumar,
Shashi Kumar:
An HOL based framework for design of correct high level synthesizers.
VLSI Design 1995: 249-254 |
1993 |
1 | | C. S. Ajay,
M. Balakrishnan,
D. Harikrishna,
M. Karunakaran,
Anshul Kumar,
Shashi Kumar,
V. Mudgil,
A. R. Naseer:
High Level Design Experiences with IDEAS.
VLSI Design 1993: 110 |