2006 |
11 | EE | Shouvik Chowdhury,
Gary William Grewal,
Dilip K. Banerji:
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times.
CCECE 2006: 1223-1227 |
2004 |
10 | | Peng Du,
Gary William Grewal,
Shawki Areibi,
Dilip K. Banerji:
A Fast Hierarchical Approach to FPGA Placement.
ESA/VLSI 2004: 497-503 |
9 | EE | Gary William Grewal,
Thomas Charles Wilson,
Ming Xu,
Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design 2004: 855-862 |
2003 |
8 | EE | Zhibin Dai,
Dilip K. Banerji:
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.
VLSI Design 2003: 85-90 |
1999 |
7 | EE | Wei Li,
Dilip K. Banerji:
Routability Prediction for Hierarchical FPGAs.
Great Lakes Symposium on VLSI 1999: 256-259 |
1996 |
6 | EE | J. Shu,
Thomas Charles Wilson,
Dilip K. Banerji:
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.
VLSI Design 1996: 73-76 |
1994 |
5 | | Thomas Charles Wilson,
Gary William Grewal,
Shawn Henshall,
Dilip K. Banerji:
An ILP-based approach to code generation.
Code Generation for Embedded Processors 1994: 103-118 |
4 | | Thomas Charles Wilson,
Gary William Grewal,
Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD 1994: 581-586 |
1993 |
3 | | Thomas Charles Wilson,
Nilanjan Mukherjee,
M. K. Garg,
Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.
VLSI Design 1993: 192-197 |
1988 |
2 | EE | M. Balakrishnan,
Arun K. Majumdar,
Dilip K. Banerji,
James G. Linders,
Jayanti C. Majithia:
Allocation of multiport memories in data path synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 536-540 (1988) |
1 | | M. Balakrishnan,
S. Sutarwala,
Arun K. Majumdar,
Dilip K. Banerji,
James G. Linders:
A Semantic Approach for Modular Synthesis of VLSI Systems.
Inf. Process. Lett. 27(1): 1-7 (1988) |