Geun Rae Cho

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2004

6 EE Geun Rae Cho, Tom Chen: Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 229-242 (2004)

2003

5 EE Geun Rae Cho, Tom Chen: Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60

4 EE Geun Rae Cho, Tom Chen: On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design 2003: 513-

2002

3 EE Geun Rae Cho, Tom Chen: On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD 2002: 322-326

2 EE Geun Rae Cho, Tom Chen: Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED 2002: 458-463

1 Geun Rae Cho, Tom Chen: On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294

2004
6	EE	Geun Rae Cho, Tom Chen: Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 229-242 (2004)
2003
5	EE	Geun Rae Cho, Tom Chen: Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60
4	EE	Geun Rae Cho, Tom Chen: On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design 2003: 513-
2002
3	EE	Geun Rae Cho, Tom Chen: On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD 2002: 322-326
2	EE	Geun Rae Cho, Tom Chen: Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED 2002: 458-463
1		Geun Rae Cho, Tom Chen: On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294

Coauthor Index

1 Tom Chen [1] [2] [3] [4] [5] [6]