| 2008 |
|---|
| 7 | EE | Jae Ug Jeong,
Soo Hwan Kim:
Sensitivity analysis for a system of generalized nonlinear mixed quasi-variational inclusions in q-uniformly smooth Banach spaces.
Applied Mathematics and Computation 202(1): 178-187 (2008) |
| 2006 |
|---|
| 6 | EE | Youngkwon Jo,
Yong Shim,
Soo Hwan Kim,
Suki Kim,
Kwanjun Cho:
A mixed-structure delay locked-loop with wide range and fast locking.
ISCAS 2006 |
| 5 | EE | Yong Shim,
Youngkwon Jo,
Soo Hwan Kim,
Suki Kim,
Kwanjun Cho:
A register controlled delay locked loop using a TDC and a new fine delay line scheme.
ISCAS 2006 |
| 4 | EE | Jae Ug Jeong,
Soo Hwan Kim:
Weak and strong convergence of the Ishikawa iteration process with errors for two asymptotically nonexpansive mappings.
Applied Mathematics and Computation 181(2): 1394-1401 (2006) |
| 2005 |
|---|
| 3 | EE | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. VLSI Syst. 13(8): 992-996 (2005) |
| 2004 |
|---|
| 2 | | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
ISCAS (2) 2004: 781-784 |
| 2003 |
|---|
| 1 | EE | Yong Sin Kim,
Soo Hwan Kim,
Kwang-Hyun Baek,
Suki Kim,
Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
VLSI Design 2003: 261- |
