2008 |
14 | | Luc Bougé,
Martti Forsell,
Jesper Larsson Träff,
Achim Streit,
Wolfgang Ziegler,
Michael Alexander,
Stephen Childs:
Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007, Revised Selected Papers
Springer 2008 |
13 | EE | Martti Forsell,
Jesper Larsson Träff:
Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008).
Euro-Par Workshops 2008: 123-125 |
12 | EE | Martti Forsell:
On the performance and cost of some PRAM models on CMP hardware.
IPDPS 2008: 1-8 |
11 | | Martti Forsell,
Jussi Roivainen:
Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures.
PDPTA 2008: 471-477 |
2007 |
10 | EE | Martti Forsell,
Jesper Larsson Träff:
HPPC 2007: Workshop on Highly Parallel Processing on a Chip.
Euro-Par Workshops 2007: 3-4 |
9 | | Martti Forsell,
Ville Leppänen:
Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC.
PDPTA 2007: 232-238 |
2005 |
8 | EE | Martti Forsell:
Realising constant time parallel algorithms with active memory modules.
IJEB 3(3/4): 255-263 (2005) |
2003 |
7 | EE | Juha-Pekka Soininen,
Axel Jantsch,
Martti Forsell,
Antti Pelkonen,
Jari Kreku,
Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems.
VLSI Design 2003: 401- |
2002 |
6 | EE | Juha-Pekka Soininen,
Jari Kreku,
Yang Qu,
Martti Forsell:
Fast processor core selection for WLAN modem using mappability estimation.
CODES 2002: 61-66 |
5 | EE | Shashi Kumar,
Axel Jantsch,
Mikael Millberg,
Johnny Öberg,
Juha-Pekka Soininen,
Martti Forsell,
Kari Tiensyrjä,
Ahmed Hemani:
A Network on Chip Architecture and Design Methodology.
ISVLSI 2002: 117-124 |
4 | EE | Martti Forsell:
A Scalable High-Performance Computing Solution for Networks on Chips.
IEEE Micro 22(5): 46-55 (2002) |
3 | EE | Eugene I. Ageenko,
Martti Forsell,
Pasi Fränti:
Context-based compression of binary images in parallel.
Softw., Pract. Exper. 32(13): 1223-1237 (2002) |
1997 |
2 | EE | Martti Forsell:
MTAC - A Multithreaded VLIW Architecture for PRAM Simulation.
J. UCS 3(9): 1037-1055 (1997) |
1996 |
1 | EE | Martti Forsell,
Martti Penttonen,
Ville Leppänen:
Efficient Two-Level Mesh based Simulation of PRAMs.
ISPAN 1996: 29-35 |