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| 2003 | ||
|---|---|---|
| 1 | EE | Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau: Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. VLSI Design 2003: 122-127 |
| 1 | A. Amerasekera | [1] |
| 2 | Sushil Gupta | [1] |
| 3 | C. B. Keshav | [1] |
| 4 | S. Krishnan | [1] |
| 5 | Vinod Menezes | [1] |
| 6 | G. Palau | [1] |