Shalini Ghosh

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7EEShalini Ghosh, Sugato Basu, Nur A. Touba: Synthesis of Low Power CED Circuits Based on Parity Codes. VTS 2005: 315-320
6EEShalini Ghosh, F. Joel Ferguson: Detection probabilities of interconnect breaks: an analysis. Integration 38(3): 451-465 (2005)
5EEShalini Ghosh, Sugato Basu, Nur A. Touba: Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. J. Low Power Electronics 1(1): 63-72 (2005)
4EEShalini Ghosh, F. Joel Ferguson: Estimating detection probability of interconnect opens using stuck-at tests. ACM Great Lakes Symposium on VLSI 2004: 254-259
3EEShalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba: Low-power weighted pseudo-random BIST using special scan cells. ACM Great Lakes Symposium on VLSI 2004: 86-91
2EEShalini Ghosh, Nur A. Touba, Sugato Basu: Reducing Power Consumption in Memory ECC Checkers. ITC 2004: 1322-1331
1EEShalini Ghosh, Sugato Basu, Nur A. Touba: Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. ISVLSI 2003: 246-249

Coauthor Index

1Sugato Basu [1] [2] [3] [5] [7]
2F. Joel Ferguson [4] [6]
3Eric MacDonald [3]
4Nur A. Touba [1] [2] [3] [5] [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)