| 2005 |
|---|
| 7 | EE | Shalini Ghosh,
Sugato Basu,
Nur A. Touba:
Synthesis of Low Power CED Circuits Based on Parity Codes.
VTS 2005: 315-320 |
| 6 | EE | Shalini Ghosh,
F. Joel Ferguson:
Detection probabilities of interconnect breaks: an analysis.
Integration 38(3): 451-465 (2005) |
| 5 | EE | Shalini Ghosh,
Sugato Basu,
Nur A. Touba:
Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits.
J. Low Power Electronics 1(1): 63-72 (2005) |
| 2004 |
|---|
| 4 | EE | Shalini Ghosh,
F. Joel Ferguson:
Estimating detection probability of interconnect opens using stuck-at tests.
ACM Great Lakes Symposium on VLSI 2004: 254-259 |
| 3 | EE | Shalini Ghosh,
Eric MacDonald,
Sugato Basu,
Nur A. Touba:
Low-power weighted pseudo-random BIST using special scan cells.
ACM Great Lakes Symposium on VLSI 2004: 86-91 |
| 2 | EE | Shalini Ghosh,
Nur A. Touba,
Sugato Basu:
Reducing Power Consumption in Memory ECC Checkers.
ITC 2004: 1322-1331 |
| 2003 |
|---|
| 1 | EE | Shalini Ghosh,
Sugato Basu,
Nur A. Touba:
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering.
ISVLSI 2003: 246-249 |
