Masato Edahiro

2009
20	EE	Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro: Dynamic security domain scaling on embedded symmetric multiprocessors. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
19	EE	Hiroaki Inoue, Junji Sakai, Masato Edahiro: Processor virtualization for secure mobile terminals. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
18	EE	Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro: FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals. ACM Trans. Embedded Comput. Syst. 8(1): (2008)
2007
17	EE	Hiroaki Inoue, Masato Edahiro, Junji Sakai: Towards scalable and secure execution platform for embedded systems. ASP-DAC 2007: 350-354
16	EE	Hiroaki Inoue, Akihisa Ikeno, Tsuyoshi Abe, Junji Sakai, Masato Edahiro: Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems. CODES+ISSS 2007: 39-44
2006
15	EE	Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro: VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals. DAC 2006: 484-489
2005
14	EE	Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro: FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. CODES+ISSS 2005: 178-183
2000
13	EE	Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi: A Single-Chip Multiprocessor for Smart Terminals. IEEE Micro 20(4): 12-20 (2000)
1998
12		Susumu Kobayashi, Masato Edahiro, Mikio Kubo: Scan-chain Optimization Algorithms for Multiple Scan-paths. ASP-DAC 1998: 301-306
11		Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi: A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs. ASP-DAC 1998: 51-56
1996
10	EE	Masato Edahiro, Richard J. Lipton: Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. Great Lakes Symposium on VLSI 1996: 143-147
9		Masato Edahiro: Equispreading Tree in Manhattan Distance. Algorithmica 16(3): 316-338 (1996)
1994
8	EE	Masato Edahiro: An Efficient Zero-Skew Routing Algorithm. DAC 1994: 375-380
1993
7	EE	Masato Edahiro: A Clustering-Based Optimization Algorithm in Zero-Skew Routings. DAC 1993: 612-616
6	EE	Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi: DCT/IDCT processor for HDTV developed with dsp silicon compiler. VLSI Signal Processing 5(2-3): 151-158 (1993)
1990
5	EE	Masato Edahiro, Takeshi Yoshimura: New Placement and Global Routing Algorithms for Standard Cell Layouts. DAC 1990: 642-645
4		Masato Edahiro: A Clock Net Reassignment Algorithm Usign Voronoi Diagram. ICCAD 1990: 420-423
1989
3		Masato Edahiro, Katsuhiko Tanaka, Takashi Hoshino, Takao Asano: A Bucketing Algorithm for the Orthogonal Segment Intersection Search Problem and Its Practical Efficiency. Algorithmica 4(1): 61-76 (1989)
1987
2	EE	Masato Edahiro, Katsuhiko Tanaka, Takashi Hoshino, Takao Asano: A Bucketing Algorithm for the Orthogonal Segment Intersection Search Problem and Its Practical Efficiency. Symposium on Computational Geometry 1987: 258-267
1984
1	EE	Masato Edahiro, I. Kokubo, Takao Asano: A New Point-Location Algorithm and Its Practical Efficiency: Comparison with Existing Algorithms. ACM Trans. Graph. 3(2): 86-109 (1984)

Coauthor Index

1	Tsuyoshi Abe	[16] [20]
2	Takao Asano	[1] [2] [3]
3	Yoshihiro Hayashi	[11]
4	Takashi Hoshino	[2] [3]
5	Akihisa Ikeno	[14] [15] [16]
6	Hiroaki Inoue	[14] [15] [16] [17] [18] [19] [20]
7	Kazuhisa Ishizaka	[20]
8	Susumu Kobayashi	[12]
9	I. Kokubo	[1]
10	Masaki Kondo	[14] [15]
11	Mikio Kubo	[12]
12	Richard J. Lipton	[10]
13	Satoshi Matsushita	[13]
14	Kaoru Mitsuhashi	[6]
15	Takashi Miyazaki	[6]
16	Naoki Nishi	[13]
17	Takao Nishitani	[6]
18	Ikuko Ono	[6]
19	Junji Sakai	[14] [15] [16] [17] [18] [19] [20]
20	Shuji Takahashi	[11]
21	Katsuhiko Tanaka	[2] [3]
22	Sunao Torii	[18]
23	Masakazu Yamashina	[13]
24	Takeshi Yoshimura	[5]

Colors in the list of coauthors