Yuzheng Ding

2008
18	EE	Jason Cong, Yuzheng Ding: FPGA Technology Mapping. Encyclopedia of Algorithms 2008
2005
17	EE	Yuzheng Ding, Peter Suaris, Nan-Chi Chou: The effect of post-layout pin permutation on timing. FPGA 2005: 41-50
2004
16	EE	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou: Incremental physical resynthesis for timing optimization. FPGA 2004: 99-108
1999
15	EE	Jason Cong, Chang Wu, Yuzheng Ding: Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA 1999: 29-35
1996
14	EE	Jason Cong, John Peck, Yuzheng Ding: RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA 1996: 137-143
13	EE	Jason Cong, Yuzheng Ding: Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996)
1995
12	EE	Jason Cong, Yuzheng Ding: On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA 1995: 82-88
1994
11	EE	Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen: LUT-based FPGA technology mapping under arbitrary net-delay models. Computers & Graphics 18(4): 507-516 (1994)
10	EE	Jason Cong, Yuzheng Ding: On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 2(2): 137-148 (1994)
9	EE	Jason Cong, Yuzheng Ding: FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 1-12 (1994)
8		Yuzheng Ding, Mark Allen Weiss: On the Complexity of Building an Interval Heap. Inf. Process. Lett. 50(3): 143-144 (1994)
1993
7	EE	Jason Cong, Yuzheng Ding: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC 1993: 213-218
6	EE	Jason Cong, Yuzheng Ding: Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD 1993: 110-114
5		Yuzheng Ding, Mark Allen Weiss: The K-D Heap: An Efficient Multi-dimensional Priority Queue. WADS 1993: 302-313
4		Yuzheng Ding, Mark Allen Weiss: The Relaxed min-max Heap. Acta Inf. 30(3): 215-231 (1993)
1992
3	EE	Jason Cong, Yuzheng Ding: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD 1992: 48-53
2		Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen: An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158
1	EE	Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar: DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers 9(3): 7-20 (1992)

Coauthor Index

1	Kuang-Chien Chen	[1] [2] [11]
2	Nan-Chi Chou	[16] [17]
3	Jason Cong	[1] [2] [3] [6] [7] [9] [10] [11] [12] [13] [14] [15] [18]
4	Tong Gao	[11]
5	Andrew B. Kahng	[1] [2]
6	Lung-Tien Liu	[16]
7	John Peck	[14]
8	Peter Suaris (Peter Ramyalal Suaris)	[16] [17]
9	Peter Trajmar	[1] [2]
10	Mark Allen Weiss	[4] [5] [8]
11	Chang Wu	[15]

Colors in the list of coauthors