| 1994 |
|---|
| 5 | | G. N. Rathna,
S. K. Nandy,
K. Parthasarathy:
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs.
VLSI Design 1994: 225-228 |
| 4 | | Debabrata Ghosh,
S. K. Nandy,
K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor.
VLSI Design 1994: 77-82 |
| 1993 |
|---|
| 3 | EE | Debabrata Ghosh,
S. K. Nandy,
P. Sadayappan,
K. Parthasarathy:
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving.
DAC 1993: 303-307 |
| 2 | | Debabrata Ghosh,
S. K. Nandy,
K. Parthasarathy,
V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
VLSI Design 1993: 341-346 |
| 1987 |
|---|
| 1 | EE | M. K. Sridhar,
R. Srinath,
K. Parthasarathy:
On the direct parallel solution of systems of linear equations: New algorithms and systolic structures.
Inf. Sci. 43(1-2): 25-53 (1987) |
