| 2006 |
|---|
| 17 | EE | C. Lac,
S. Ramanathan:
A Resilient Telco Grid Middleware.
ISCC 2006: 306-311 |
| 2000 |
|---|
| 16 | EE | S. Ramanathan,
S. K. Nandy,
V. Visvanathan:
Reconfigurable Filter Coprocessor Architecture for DSP Applications.
VLSI Signal Processing 26(3): 333-359 (2000) |
| 1999 |
|---|
| 15 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Synthesis of Configurable Architectures for DSP Algorithms.
VLSI Design 1999: 350-357 |
| 14 | EE | S. Ramanathan,
V. Visvanathan:
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1.
Integration 27(1): 1-32 (1999) |
| 13 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Synthesis of ASIPs for DSP algorithms.
Integration 28(1): 13-32 (1999) |
| 12 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering.
VLSI Signal Processing 22(3): 173-195 (1999) |
| 11 | EE | S. Ramanathan:
A unified framework and algorithm for channel assignment in wireless networks.
Wireless Networks 5(2): 81-94 (1999) |
| 1997 |
|---|
| 10 | | S. Ramanathan:
A Unified Framework and Algorithm for (T/F/C)DMA Channel Assignment in Wireless Networks.
INFOCOM 1997: 900-907 |
| 9 | EE | S. Ramanathan,
V. Visvanathan:
Low-Power Configurable Processor Array for DLMS Adaptive Filtering.
VLSI Design 1997: 198-207 |
| 1996 |
|---|
| 8 | EE | S. Ramanathan,
V. Visvanathan:
A systolic architecture for LMS adaptive filtering with minimal adaptation delay.
VLSI Design 1996: 286-289 |
| 7 | EE | S. Ramanathan:
Multicast tree generation in networks with asymmetric links.
IEEE/ACM Trans. Netw. 4(4): 558-568 (1996) |
| 6 | | S. Ramanathan,
Martha Steenstrup:
Editorial: Routing in Mobile Communications Networks.
MONET 1(2): 87-88 (1996) |
| 5 | | S. Ramanathan,
Martha Steenstrup:
A Survey of Routing Techniques for Mobile Communications Networks.
MONET 1(2): 89-104 (1996) |
| 1995 |
|---|
| 4 | EE | V. Visvanathan,
S. Ramanathan:
A modular systolic architecture for delayed least mean squares adaptive filtering.
VLSI Design 1995: 332-337 |
| 1993 |
|---|
| 3 | | V. Visvanathan,
Nibedita Mohanty,
S. Ramanathan:
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters.
VLSI Design 1993: 166-171 |
| 2 | | S. Ramanathan,
Nibedita Mohanty,
V. Visvanathan:
A Methodology for Generating Application Specific Tree Multipliers.
VLSI Design 1993: 176-179 |
| 1990 |
|---|
| 1 | | S. Ramanathan,
G. Sivakumar:
Rewrite Systems for Protocol Specification and Verification.
FORTE 1990: 79-94 |
