| 2004 |
|---|
| 11 | EE | Gary William Grewal,
Thomas Charles Wilson,
Ming Xu,
Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design 2004: 855-862 |
| 2003 |
|---|
| 10 | EE | Gary William Grewal,
Thomas Charles Wilson:
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
International Journal of Computational Intelligence and Applications 3(1): 45-64 (2003) |
| 2002 |
|---|
| 9 | EE | Gary William Grewal,
Thomas Charles Wilson,
Christopher W. Nell:
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
Canadian Conference on AI 2002: 325-333 |
| 2001 |
|---|
| 8 | EE | Gary William Grewal,
Thomas Charles Wilson:
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T).
MICRO 2001: 192-202 |
| 7 | | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
International Journal of Computational Intelligence and Applications 1(1): 91-110 (2001) |
| 1997 |
|---|
| 6 | EE | Thomas Charles Wilson,
Gary William Grewal:
Shake And Bake: A Method of Mapping Code to Irregular DSPs.
VLSI Design 1997: 506-508 |
| 5 | EE | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
VLSI Design 1997: 51-56 |
| 1996 |
|---|
| 4 | EE | J. Shu,
Thomas Charles Wilson,
Dilip K. Banerji:
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.
VLSI Design 1996: 73-76 |
| 1994 |
|---|
| 3 | | Thomas Charles Wilson,
Gary William Grewal,
Shawn Henshall,
Dilip K. Banerji:
An ILP-based approach to code generation.
Code Generation for Embedded Processors 1994: 103-118 |
| 2 | | Thomas Charles Wilson,
Gary William Grewal,
Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD 1994: 581-586 |
| 1993 |
|---|
| 1 | | Thomas Charles Wilson,
Nilanjan Mukherjee,
M. K. Garg,
Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.
VLSI Design 1993: 192-197 |
