| 2006 |
|---|
| 14 | EE | Shouvik Chowdhury,
Gary William Grewal,
Dilip K. Banerji:
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times.
CCECE 2006: 1223-1227 |
| 2004 |
|---|
| 13 | | Peng Du,
Gary William Grewal,
Shawki Areibi,
Dilip K. Banerji:
A Fast Hierarchical Approach to FPGA Placement.
ESA/VLSI 2004: 497-503 |
| 12 | | Gary William Grewal,
Ming Xu,
Charlie Obimbo:
An Approximate Solution for Steiner Trees in Multicast Routing.
IC-AI 2004: 707-711 |
| 11 | EE | Gary William Grewal,
Thomas Charles Wilson,
Ming Xu,
Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design 2004: 855-862 |
| 2003 |
|---|
| 10 | | Gary William Grewal,
Mike O'Cleirigh,
Charlie Obimbo:
Hierarchical Genetic Algorithms Applied to Datapath Synthesis.
IC-AI 2003: 994-1002 |
| 9 | EE | Gary William Grewal,
Thomas Charles Wilson:
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
International Journal of Computational Intelligence and Applications 3(1): 45-64 (2003) |
| 2002 |
|---|
| 8 | EE | Gary William Grewal,
Thomas Charles Wilson,
Christopher W. Nell:
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
Canadian Conference on AI 2002: 325-333 |
| 2001 |
|---|
| 7 | EE | Gary William Grewal,
Thomas Charles Wilson:
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T).
MICRO 2001: 192-202 |
| 6 | | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
International Journal of Computational Intelligence and Applications 1(1): 91-110 (2001) |
| 1997 |
|---|
| 5 | EE | Thomas Charles Wilson,
Gary William Grewal:
Shake And Bake: A Method of Mapping Code to Irregular DSPs.
VLSI Design 1997: 506-508 |
| 4 | EE | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
VLSI Design 1997: 51-56 |
| 1996 |
|---|
| 3 | EE | Gary William Grewal:
A Global Mode Instruction Minimization Technique for Embedded DSPs.
Great Lakes Symposium on VLSI 1996: 18- |
| 1994 |
|---|
| 2 | | Thomas Charles Wilson,
Gary William Grewal,
Shawn Henshall,
Dilip K. Banerji:
An ILP-based approach to code generation.
Code Generation for Embedded Processors 1994: 103-118 |
| 1 | | Thomas Charles Wilson,
Gary William Grewal,
Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD 1994: 581-586 |
