R. V. Raj
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1997
1
EE
R. V. Raj,
N. S. Murty
,
P. S. Nagendra Rao
,
Lalit M. Patnaik
: Effective Heuristics for Timing Driven Constructive Placement.
VLSI Design 1997
: 38-45
Coauthor
Index
1
N. S. Murty
[
1
]
2
Lalit M. Patnaik
[
1
]
3
P. S. Nagendra Rao
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)