| 2008 |
|---|
| 15 | EE | Ahmed Abdallah,
Wayne Wolf,
Graham R. Hellestrand:
Statistical characterization of execution time through simulation.
WISES 2008: 1-13 |
| 2005 |
|---|
| 14 | EE | Graham R. Hellestrand:
Systems architecture: the empirical way: abstract architectures to 'optimal' systems.
EMSOFT 2005: 147-158 |
| 13 | | Graham R. Hellestrand:
The Engineering of Supersystems.
IEEE Computer 38(1): 103-105 (2005) |
| 1999 |
|---|
| 12 | EE | Graham R. Hellestrand:
Designing system on a chip products using systems engineering tools.
ISCAS (6) 1999: 468-473 |
| 1997 |
|---|
| 11 | EE | Radhakrishna Nagalla,
Graham R. Hellestrand:
A Visual Approach for Asynchronous Circuit Synthesis.
VLSI Design 1997: 329-335 |
| 1996 |
|---|
| 10 | EE | Tommy King-Yin Cheung,
Graham R. Hellestrand,
Prasert Kanthamanon:
A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study.
CODES 1996: 10-17 |
| 9 | EE | Radhakrishna Nagalla,
Graham R. Hellestrand:
Elimination of Dynamic Hazards from Signal Transition Graphs.
VLSI Design 1996: 382-388 |
| 1995 |
|---|
| 8 | EE | Morteza Saheb Zamani,
Graham R. Hellestrand:
A neural network approach to the placement problem.
ASP-DAC 1995 |
| 7 | | Michael C. Doggett,
Graham R. Hellestrand:
A Hardware Architecture for Video Rate Shading of Volume Data.
ISCAS 1995: 433-436 |
| 6 | | Morteza Saheb Zamani,
Graham R. Hellestrand:
A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs.
ISCAS 1995: 49-52 |
| 5 | | Morteza Saheb Zamani,
Graham R. Hellestrand:
A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs.
IWANN 1995: 1128-1134 |
| 4 | EE | Michael C. Doggett,
Graham R. Hellestrand:
A hardware architecture for video rate smooth shading of volume data.
Computers & Graphics 19(5): 695-704 (1995) |
| 1994 |
|---|
| 3 | | Mehdi N. Fesharaki,
Graham R. Hellestrand:
A Real-Time Edge Detection ASIC Design.
ISCAS 1994: 81-84 |
| 2 | | Radhakrishna Nagalla,
Graham R. Hellestrand:
Signal Transition Graph Constraints for Synthesis of Hazard-Free Asynchronous Circuits with Unbounded-Gate Delays.
Formal Methods in System Design 5(3): 245-273 (1994) |
| 1991 |
|---|
| 1 | EE | M. A. Bickerstaff,
Graham R. Hellestrand:
A highly parallel architecture for real time collision detection in flight simulation.
Computers & Graphics 15(3): 355-363 (1991) |
