| 2007 |
|---|
| 12 | EE | Fu-Chiung Cheng,
Shu-Ming Chang,
Chi-Huam Shieh:
Detection and Generation of Self-Timed Pipelines from High Level Specifications.
VLSI Design 2007: 413-418 |
| 2006 |
|---|
| 11 | EE | Fu-Chiung Cheng,
Hung-Chi Wu:
Design and Implementation of Software Objects in Hardware.
ICCD 2006 |
| 10 | EE | Fu-Chiung Cheng,
Tai-Chang Hung,
Young-Jang Chiou:
Analysis, Design and Implementation of Exception Handling in WWW Services.
SOSE 2006: 102-109 |
| 2005 |
|---|
| 9 | EE | Li-Kai Chang,
Fu-Chiung Cheng:
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits.
ICCD 2005: 289-296 |
| 2001 |
|---|
| 8 | | Fu-Chiung Cheng,
Shuen-Long Ho:
Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission.
ICCD 2001: 24-31 |
| 2000 |
|---|
| 7 | EE | Fu-Chiung Cheng,
Chuin-Ren Wang:
Specification and Design of a Quasi-Delay-Insensitive Java Card.
VLSI Design 2000: 356-361 |
| 6 | EE | Fu-Chiung Cheng,
Stephen H. Unger,
Michael Theobald:
Self-Timed Carry-Lookahead Adders.
IEEE Trans. Computers 49(7): 659-672 (2000) |
| 1997 |
|---|
| 5 | | Fu-Chiung Cheng:
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits.
ICCD 1997: 301-306 |
| 4 | EE | Fu-Chiung Cheng,
Stephen H. Unger,
Michael Theobald,
Wen-Chung Cho:
Delay-Insensitive Carry-Lookahead Adders.
VLSI Design 1997: 322-328 |
| 3 | EE | Steven M. Nowick,
Niraj K. Jha,
Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1514-1521 (1997) |
| 1995 |
|---|
| 2 | EE | Steven M. Nowick,
Niraj K. Jha,
Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
VLSI Design 1995: 171-176 |
| 1990 |
|---|
| 1 | EE | Fu-Chiung Cheng,
Huei-Huang Chen,
Jiin-Hwai Perng:
Parallel execution on production systems.
SPDP 1990: 463-470 |
