| 2001 |
|---|
| 5 | EE | Jason Cong,
Tianming Kong,
Z. D. Pan:
Buffer block planning for interconnect planning and prediction.
IEEE Trans. VLSI Syst. 9(6): 929-937 (2001) |
| 2000 |
|---|
| 4 | EE | Jason Cong,
Tianming Kong,
Faming Liang,
Jun S. Liu,
Wing Hung Wong,
Dongmin Xu:
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application.
ASP-DAC 2000: 277-282 |
| 3 | | Tony F. Chan,
Jason Cong,
Tianming Kong,
Joseph R. Shinnerl:
Multilevel Optimization for Large-Scale Circuit Placement.
ICCAD 2000: 171-176 |
| 1999 |
|---|
| 2 | EE | Jason Cong,
Tianming Kong,
Dongmin Xu,
Faming Liang,
Jun S. Liu,
Wing Hung Wong:
Relaxed Simulated Tempering for VLSI Floorplan Designs.
ASP-DAC 1999: 13-16 |
| 1 | EE | Jason Cong,
Tianming Kong,
David Zhigang Pan:
Buffer block planning for interconnect-driven floorplanning.
ICCAD 1999: 358-363 |
