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| 2000 | ||
|---|---|---|
| 2 | EE | Jiangchun Gu, Zeyi Wang, Xianlong Hong: Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. ASP-DAC 2000: 447-452 |
| 1 | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12 | |
| 1 | Yici Cai | [1] |
| 2 | Chung-Kuan Cheng | [1] |
| 3 | Sheqin Dong | [1] |
| 4 | Jun Gu | [1] |
| 5 | Xianlong Hong | [1] [2] |
| 6 | Gang Huang | [1] |
| 7 | Zeyi Wang | [2] |