2004 | ||
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4 | EE | Satrajit Gupta, Lawrence T. Pileggi: CHIME: coupled hierarchical inductance model evaluation. DAC 2004: 800-805 |
2000 | ||
3 | Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi: Hierarchical Interconnect Circuit Models. ICCAD 2000: 215-221 | |
1999 | ||
2 | EE | Satrajit Gupta, Lalit M. Patnaik: Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms. VLSI Design 1999: 160-163 |
1 | EE | M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale: Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design 1999: 340-345 |
1 | Michael W. Beattie | [3] |
2 | M. N. Mahesh | [1] |
3 | Mahesh Mehendale | [1] |
4 | Lalit M. Patnaik | [2] |
5 | Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage) | [3] [4] |