Volume 1,
Number 1,
April 2005
Editorial
Research Articles
- Christian Schuster, Christian Piguet, Jean-Luc Nagel, Pierre-André Farine:
An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.
3-10
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- Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia:
Selective Clock-Gating for Low-Power Synchronous Counters.
11-19
Electronic Edition (link) BibTeX
- Alin Razafindraibe, Michel Robert, Philippe Maurine:
Compact and Secured Primitives for the Design of Asynchronous Circuits.
20-26
Electronic Edition (link) BibTeX
- Kihwan Choi, Wei-Chung Cheng, Massoud Pedram:
Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player.
27-43
Electronic Edition (link) BibTeX
- Kihwan Choi, Kwanho Kim, Massoud Pedram:
Energy-Aware MPEG-4 FGS Streaming.
44-51
Electronic Edition (link) BibTeX
- Hyung Gyu Lee, Naehyuck Chang:
Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems.
52-62
Electronic Edition (link) BibTeX
- Shalini Ghosh, Sugato Basu, Nur A. Touba:
Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits.
63-72
Electronic Edition (link) BibTeX
- Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, Subramanian Chebiyam:
Power and Design for Test: A Design Automation Perspective.
73-84
Electronic Edition (link) BibTeX
- Patrick Girard, Yannick Bonhomme:
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
85-95
Electronic Edition (link) BibTeX
Volume 1,
Number 2,
August 2005
Research Articles
- Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh:
Epsilon-Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems.
97-107
Electronic Edition (link) BibTeX
- Arindam Mallik, Gokhan Memik:
Low Power Correlating Caches for Network Processors.
108-118
Electronic Edition (link) BibTeX
- Julien Lamoureux, Steven J. E. Wilton:
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays.
119-132
Electronic Edition (link) BibTeX
- Chang Woo Kang, Massoud Pedram:
A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect.
133-144
Electronic Edition (link) BibTeX
- Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Pseudo Dual Supply Voltage Domino Logic Design.
145-152
Electronic Edition (link) BibTeX
- Olivier Mazouffre, Hervé Lapuyade, Jean-Baptiste Begueret, Andreia Cathelin, Didier Belot, Yann Deval:
A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler.
153-160
Electronic Edition (link) BibTeX
- Jingzhao Ou, Viktor K. Prasanna:
Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors.
161-171
Electronic Edition (link) BibTeX
- Emrah Acar, Anirudh Devgan, Sani R. Nassif:
Leakage and Leakage Sensitivity Computation for Combinational Circuits.
172-181
Electronic Edition (link) BibTeX
- Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar:
Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits.
182-193
Electronic Edition (link) BibTeX
- Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Low Power Test Generation for Path Delay Faults.
194-205
Electronic Edition (link) BibTeX
Volume 1,
Number 3,
December 2005
Research Articles
- Woonseok Kim, Dongkun Shin, Han-Saem Yun, Jihong Kim, Sang Lyul Min:
Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems.
207-216
Electronic Edition (link) BibTeX
- Arindam Calomarde, Antonio Rubio, Jordi Saludes:
Selective Clock-Gating for Low-Power Synchronous Counters.
217-225
Electronic Edition (link) BibTeX
- Chantal Ykman-Couvreur, Francky Catthoor, Johan Vounckx, Andy Folens, Filip Louagie:
Energy-aware Dynamic Task Scheduling Applied to a Real-time Multimedia Application on an Xscale Board.
226-237
Electronic Edition (link) BibTeX
- Yan Meng, Wenrui Gong, Ryan Kastner, Timothy Sherwood:
Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator.
238-248
Electronic Edition (link) BibTeX
- Victor F. Gomes, Antonio Carlos Schneider Beck, Luigi Carro:
Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging.
249-258
Electronic Edition (link) BibTeX
- Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee:
High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits.
259-272
Electronic Edition (link) BibTeX
- Eren Kursun, Rajarshi Mukherjee, Seda Ogrenci Memik:
Early Quality Assessment for Low Power Behavioral Synthesis.
273-285
Electronic Edition (link) BibTeX
- Dhireesha Kudithipudi, Eugene John:
Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks.
286-296
Electronic Edition (link) BibTeX
- Weiping Liao, Lei He:
Microarchitecture Level Interconnect Modeling Considering Layout Optimization.
297-308
Electronic Edition (link) BibTeX
- Mauro Olivieri, Simone Smorfa, Alessandro Trifiletti:
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips.
309-318
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- Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction.
319-330
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:10:39 2009
by Michael Ley (ley@uni-trier.de)
