| 2008 |
|---|
| 59 | EE | Raymond G. Beausoleil,
J. Ahn,
Nathan L. Binkert,
Al Davis,
D. Fattal,
Marco Fiorentino,
Norman P. Jouppi,
Moray McLaren,
C. M. Santori,
R. S. Schreiber,
S. M. Spillane,
Dana Vantrease,
Q. Xu:
A Nanophotonic Interconnect for High-Performance Many-Core Computation.
Hot Interconnects 2008: 182-189 |
| 58 | EE | Michael Tan,
Paul Rosenberg,
Jong Souk Yeo,
Moray McLaren,
Sagi Mathai,
Terry Morris,
Joseph Straznicky,
Norman P. Jouppi,
Huei Pei Kuo,
Shih-Yuan Wang,
Scott Lerner,
Pavel Kornilovich,
Neal Meyer,
Robert Bicknell,
Charles Otis,
Len Seals:
A High-Speed Optical Multi-Drop Bus for Computer Interconnections.
Hot Interconnects 2008: 3-10 |
| 57 | EE | Dana Vantrease,
Robert Schreiber,
Matteo Monchiero,
Moray McLaren,
Norman P. Jouppi,
Marco Fiorentino,
Al Davis,
Nathan L. Binkert,
Raymond G. Beausoleil,
Jung Ho Ahn:
Corona: System Implications of Emerging Nanophotonic Technology.
ISCA 2008: 153-164 |
| 56 | EE | Shyamkumar Thoziyoor,
Jung Ho Ahn,
Matteo Monchiero,
Jay B. Brockman,
Norman P. Jouppi:
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.
ISCA 2008: 51-62 |
| 55 | EE | Norman P. Jouppi:
System implications of integrated photonics.
ISLPED 2008: 183-184 |
| 54 | EE | Nidhi Aggarwal,
James E. Smith,
Kewal K. Saluja,
Norman P. Jouppi,
Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache.
MICRO 2008: 71-82 |
| 53 | EE | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
IEEE Micro 28(1): 69-79 (2008) |
| 2007 |
|---|
| 52 | EE | Shekhar Borkar,
Norman P. Jouppi,
Per Stenström:
Microprocessors in the era of terascale integration.
DATE 2007: 237-242 |
| 51 | EE | Nidhi Aggarwal,
Parthasarathy Ranganathan,
Norman P. Jouppi,
James E. Smith:
Configurable isolation: building high availability systems with commodity multi-core processors.
ISCA 2007: 470-481 |
| 50 | EE | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
MICRO 2007: 3-14 |
| 49 | EE | Michael S. Schlansker,
Nagabhushan Chitlur,
Erwin Oertli,
Paul M. Stillwell Jr.,
Linda Rankin,
Dennis Bradford,
Richard J. Carter,
Jayaram Mudigonda,
Nathan L. Binkert,
Norman P. Jouppi:
High-performance ethernet-based communications for future multi-core processors.
SC 2007: 37 |
| 48 | EE | Nidhi Aggarwal,
Parthasarathy Ranganathan,
Norman P. Jouppi,
James E. Smith:
Isolation in Commodity Multicore Processors.
IEEE Computer 40(6): 49-59 (2007) |
| 2006 |
|---|
| 47 | EE | Anahita Shayesteh,
Glenn Reinman,
Norman P. Jouppi,
Timothy Sherwood,
Suleyman Sair:
Improving the performance and power efficiency of shared helpers in CMPs.
CASES 2006: 345-356 |
| 46 | EE | Jack Sampson,
Rubén González,
Jean-Francois Collard,
Norman P. Jouppi,
Michael S. Schlansker,
Brad Calder:
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.
MICRO 2006: 235-246 |
| 45 | EE | Rakesh Kumar,
Dean M. Tullsen,
Norman P. Jouppi:
Core architecture optimization for heterogeneous chip multiprocessors.
PACT 2006: 23-32 |
| 44 | EE | Christophe Lemuet,
Jack Sampson,
Jean-Francois Collard,
Norman P. Jouppi:
Architecture - The potential energy efficiency of vector acceleration.
SC 2006: 77 |
| 2005 |
|---|
| 43 | EE | Parthasarathy Ranganathan,
Norman P. Jouppi:
Enterprise IT Trends and Implications for Architecture Research.
HPCA 2005: 253-256 |
| 42 | | Norman P. Jouppi,
Stan Thomas:
Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation.
ICRA 2005: 62-68 |
| 41 | EE | Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors.
MICRO 2005: 155 |
| 40 | EE | Jean-Francois Collard,
Norman P. Jouppi,
Sami Yehia:
System-wide performance monitors and their application to the optimization of coherent memory accesses.
PPOPP 2005: 247-254 |
| 39 | EE | Rakesh Kumar,
Dean M. Tullsen,
Norman P. Jouppi,
Parthasarathy Ranganathan:
Heterogeneous Chip Multiprocessors.
IEEE Computer 38(11): 32-38 (2005) |
| 38 | EE | Norman P. Jouppi,
Rakesh Kumar,
Dean M. Tullsen:
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).
SIGARCH Computer Architecture News 33(4): 4 (2005) |
| 37 | EE | Jack Sampson,
Rubén González,
Jean-Francois Collard,
Norman P. Jouppi,
Michael S. Schlansker:
Fast synchronization for chip multiprocessors.
SIGARCH Computer Architecture News 33(4): 64-69 (2005) |
| 36 | EE | Anahita Shayesteh,
Glenn Reinman,
Norman P. Jouppi,
Suleyman Sair,
Timothy Sherwood:
Dynamically configurable shared CMP helper engines for improved performance.
SIGARCH Computer Architecture News 33(4): 70-79 (2005) |
| 2004 |
|---|
| 35 | EE | Norman P. Jouppi,
Subu Iyer,
Stan Thomas,
April Slayden:
BiReality: mutually-immersive telepresence.
ACM Multimedia 2004: 860-867 |
| 34 | EE | Norman P. Jouppi:
The Future Evolution of High-Performance Microprocessors.
HiPC 2004: 5 |
| 33 | | Jacob Augustine,
Shivarama Rao,
Norman P. Jouppi,
Subu Iyer:
Region of interest editing of MPEG-2 video streams in the compressed domain.
ICME 2004: 559-562 |
| 32 | EE | Norman P. Jouppi,
Subu Iyer,
Wayne Mack,
April Slayden Mitchell,
Stan Thomas:
A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking.
ICRA 2004: 1670-1675 |
| 31 | EE | Rakesh Kumar,
Dean M. Tullsen,
Parthasarathy Ranganathan,
Norman P. Jouppi,
Keith I. Farkas:
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.
ISCA 2004: 64-75 |
| 30 | EE | Rakesh Kumar,
Norman P. Jouppi,
Dean M. Tullsen:
Conjoined-Core Chip Multiprocessing.
MICRO 2004: 195-206 |
| 2003 |
|---|
| 29 | EE | Rakesh Kumar,
Keith I. Farkas,
Norman P. Jouppi,
Parthasarathy Ranganathan,
Dean M. Tullsen:
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.
MICRO 2003: 81-92 |
| 28 | EE | Rakesh Kumar,
Keith I. Farkas,
Norman P. Jouppi,
Parthasarathy Ranganathan,
Dean M. Tullsen:
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.
Computer Architecture Letters 2: (2003) |
| 2002 |
|---|
| 27 | EE | Norman P. Jouppi:
First steps towards mutually-immersive mobile telepresence.
CSCW 2002: 354-363 |
| 26 | EE | M. S. Hrishikesh,
Doug Burger,
Stephen W. Keckler,
Premkishore Shivakumar,
Norman P. Jouppi,
Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
ISCA 2002: 14-24 |
| 2000 |
|---|
| 25 | EE | Parthasarathy Ranganathan,
Sarita V. Adve,
Norman P. Jouppi:
Reconfigurable caches and their application to media processing.
ISCA 2000: 214-224 |
| 1999 |
|---|
| 24 | EE | Parthasarathy Ranganathan,
Sarita V. Adve,
Norman P. Jouppi:
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions.
ISCA 1999: 124-135 |
| 23 | EE | Joel McCormack,
Ronald N. Perry,
Keith I. Farkas,
Norman P. Jouppi:
Feline: Fast Elliptical Lines for Anisotropic Texture Mapping.
SIGGRAPH 1999: 243-250 |
| 22 | | Keith I. Farkas,
Paul Chow,
Norman P. Jouppi,
Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.
International Journal of Parallel Programming 27(5): 327-356 (1999) |
| 1998 |
|---|
| 21 | EE | Norman P. Jouppi:
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers.
25 Years ISCA: Retrospectives and Reprints 1998: 388-397 |
| 20 | EE | Norman P. Jouppi:
Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.
25 Years ISCA: Retrospectives and Reprints 1998: 71-73 |
| 1997 |
|---|
| 19 | EE | Keith I. Farkas,
Paul Chow,
Norman P. Jouppi,
Zvonko G. Vranesic:
Memory-System Design Considerations for Dynamically-Scheduled Processors.
ISCA 1997: 133-143 |
| 18 | EE | Subbarao Palacharla,
Norman P. Jouppi,
James E. Smith:
Complexity-Effective Superscalar Processors.
ISCA 1997: 206-218 |
| 17 | EE | Keith I. Farkas,
Paul Chow,
Norman P. Jouppi,
Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
MICRO 1997: 149-159 |
| 1996 |
|---|
| 16 | EE | Keith I. Farkas,
Norman P. Jouppi,
Paul Chow:
Register File Design Considerations in Dynamically Scheduled Processors.
HPCA 1996: 40-51 |
| 1995 |
|---|
| 15 | | Keith I. Farkas,
Norman P. Jouppi,
Paul Chow:
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?
HPCA 1995: 78-89 |
| 1994 |
|---|
| 14 | | Keith I. Farkas,
Norman P. Jouppi:
Complexity/Performance Tradeoffs with Non-Blocking Loads.
ISCA 1994: 211-222 |
| 13 | | Norman P. Jouppi,
Steven J. E. Wilton:
Tradeoffs in Two-Level On-Chip Caching.
ISCA 1994: 34-45 |
| 1993 |
|---|
| 12 | | Norman P. Jouppi:
Cache Write Policies and Performance.
ISCA 1993: 191-201 |
| 1992 |
|---|
| 11 | | J. Bradley Chen,
Anita Borg,
Norman P. Jouppi:
A Simulation Based Study of TLB Performance.
ISCA 1992: 114-123 |
| 1991 |
|---|
| 10 | | John L. Hennessy,
Norman P. Jouppi:
Computer Technology and Architecture: An Evolving Interaction.
IEEE Computer 24(9): 18-29 (1991) |
| 1990 |
|---|
| 9 | | Norman P. Jouppi:
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.
ISCA 1990: 364-373 |
| 1989 |
|---|
| 8 | | Norman P. Jouppi,
Jonathan Bertoni,
David W. Wall:
A Unified Vector/Scalar Floating-Point Architecture.
ASPLOS 1989: 134-143 |
| 7 | | Norman P. Jouppi,
David W. Wall:
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.
ASPLOS 1989: 272-282 |
| 6 | EE | Norman P. Jouppi:
Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU.
ISCA 1989: 281-289 |
| 5 | | Norman P. Jouppi:
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.
IEEE Trans. Computers 38(12): 1645-1658 (1989) |
| 1987 |
|---|
| 4 | EE | Norman P. Jouppi:
Derivation of Signal Flow Direction in MOS VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 480-490 (1987) |
| 3 | EE | Norman P. Jouppi:
Timing Analysis and Performance Improvement of MOS VLSI Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 650-665 (1987) |
| 1982 |
|---|
| 2 | | John L. Hennessy,
Norman P. Jouppi,
Forest Baskett,
Thomas R. Gross,
John Gill:
Hardware/Software Tradeoffs for Increased Performance.
ASPLOS 1982: 2-11 |
| 1 | | John L. Hennessy,
Norman P. Jouppi,
John Gill,
Forest Baskett,
Alex Strong,
Thomas R. Gross,
Christopher Rowen,
Judson Leonard:
The MIPS Machine.
COMPCON 1982: 2-7 |
