| |
| 1995 | ||
|---|---|---|
| 3 | EE | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja: An optimized testable architecture for finite state machines. VTS 1995: 164-169 |
| 1993 | ||
| 2 | EE | Chun-Yeh Liu, Kewal K. Saluja: An efficient algorithm for bipartite PLA folding. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1839-1847 (1993) |
| 1987 | ||
| 1 | EE | Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya: BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. DAC 1987: 385-391 |
| 1 | Ting-Yu Kuo | [3] |
| 2 | Kewal K. Saluja | [1] [2] [3] |
| 3 | Shambhu J. Upadhyaya | [1] |