| 2009 |
|---|
| 88 | EE | Philip M. Wells,
Koushik Chakraborty,
Gurindar S. Sohi:
Mixed-mode multicore reliability.
ASPLOS 2009: 169-180 |
| 87 | EE | Matthew D. Allen,
Srinath Sridharan,
Gurindar S. Sohi:
Serialization sets: a dynamic dependence-based parallel execution model.
PPOPP 2009: 85-96 |
| 2008 |
|---|
| 86 | EE | Philip M. Wells,
Koushik Chakraborty,
Gurindar S. Sohi:
Adapting to intermittent faults in multicore systems.
ASPLOS 2008: 255-264 |
| 85 | EE | Philip M. Wells,
Gurindar S. Sohi:
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again.
HPCA 2008: 264-275 |
| 2007 |
|---|
| 84 | EE | Jichuan Chang,
Gurindar S. Sohi:
Cooperative cache partitioning for chip multiprocessors.
ICS 2007: 242-252 |
| 83 | EE | Philip M. Wells,
Koushik Chakraborty,
Gurindar S. Sohi:
Adapting to Intermittent Faults in Future Multicore Systems.
PACT 2007: 431 |
| 2006 |
|---|
| 82 | EE | Koushik Chakraborty,
Philip M. Wells,
Gurindar S. Sohi:
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly.
ASPLOS 2006: 283-292 |
| 81 | EE | Jichuan Chang,
Gurindar S. Sohi:
Cooperative Caching for Chip Multiprocessors.
ISCA 2006: 264-276 |
| 80 | EE | Saisanthosh Balakrishnan,
Gurindar S. Sohi:
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs.
ISCA 2006: 302-313 |
| 79 | EE | Philip M. Wells,
Koushik Chakraborty,
Gurindar S. Sohi:
Hardware support for spin management in overcommitted virtual machines.
PACT 2006: 124-133 |
| 2004 |
|---|
| 78 | EE | Jaehyuk Huh,
Jichuan Chang,
Doug Burger,
Gurindar S. Sohi:
Coherence decoupling: making use of incoherence.
ASPLOS 2004: 97-106 |
| 77 | EE | J. Adam Butts,
Gurindar S. Sohi:
Use-Based Register Caching with Decoupled Indexing.
ISCA 2004: 302-313 |
| 76 | | Gurindar S. Sohi:
Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation.
MICRO 2004: 143 |
| 75 | EE | Jaehyuk Huh,
Doug Burger,
Jichuan Chang,
Gurindar S. Sohi:
Speculative Incoherent Cache Protocols.
IEEE Micro 24(6): 104-109 (2004) |
| 2003 |
|---|
| 74 | EE | Paramjit S. Oberoi,
Gurindar S. Sohi:
Parallelism in the Front-End.
ISCA 2003: 230-240 |
| 73 | EE | Saisanthosh Balakrishnan,
Gurindar S. Sohi:
Exploiting Value Locality in Physical Register Files.
MICRO 2003: 265-276 |
| 2002 |
|---|
| 72 | EE | J. Adam Butts,
Gurindar S. Sohi:
Dynamic dead-instruction detection and elimination.
ASPLOS 2002: 199-210 |
| 71 | EE | Paramjit S. Oberoi,
Gurindar S. Sohi:
Out-of-Order Instruction Fetch Using Multiple Sequencers.
ICPP 2002: 14- |
| 70 | EE | J. Adam Butts,
Gurindar S. Sohi:
Characterizing and predicting value degree of use.
MICRO 2002: 15-26 |
| 69 | EE | Amir Roth,
Gurindar S. Sohi:
A quantitative framework for automated pre-execution thread selection.
MICRO 2002: 430-441 |
| 68 | EE | Craig B. Zilles,
Gurindar S. Sohi:
Master/slave speculative parallelization.
MICRO 2002: 85-96 |
| 67 | EE | Andreas Moshovos,
Gurindar S. Sohi:
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction.
IEEE Trans. Computers 51(3): 313-326 (2002) |
| 2001 |
|---|
| 66 | EE | Craig B. Zilles,
Gurindar S. Sohi:
A Programmable Co-Processor for Profiling.
HPCA 2001: 241- |
| 65 | EE | Amir Roth,
Gurindar S. Sohi:
Speculative Data-Driven Multithreading.
HPCA 2001: 37- |
| 64 | EE | Craig B. Zilles,
Gurindar S. Sohi:
Execution-based prediction using speculative slices.
ISCA 2001: 2-13 |
| 63 | EE | Gurindar S. Sohi:
Microprocessors - 10 Years Back, 10 Years Ahead.
Informatics 2001: 209-218 |
| 62 | EE | Gurindar S. Sohi,
Amir Roth:
Speculative Multithreaded Processors.
IEEE Computer 34(4): 66-71 (2001) |
| 61 | EE | T. N. Vijaykumar,
Sridhar Gopal,
James E. Smith,
Gurindar S. Sohi:
Speculative Versioning Cache.
IEEE Trans. Parallel Distrib. Syst. 12(12): 1305-1317 (2001) |
| 60 | EE | Amir Roth,
Gurindar S. Sohi:
Squash Reuse via a Simplified Implementation of Register Integration.
J. Instruction-Level Parallelism 3: (2001) |
| 2000 |
|---|
| 59 | EE | Andreas Moshovos,
Gurindar S. Sohi:
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors.
HPCA 2000: 301-312 |
| 58 | EE | Gurindar S. Sohi:
Amir Roth: Speculative Multithreaded Processors.
HiPC 2000: 259-270 |
| 57 | EE | Craig B. Zilles,
Gurindar S. Sohi:
Understanding the backward slices of performance degrading instructions.
ISCA 2000: 172-181 |
| 56 | EE | J. Adam Butts,
Gurindar S. Sohi:
A static power model for architects.
MICRO 2000: 191-201 |
| 55 | EE | Amir Roth,
Gurindar S. Sohi:
Register integration: a simple and efficient implementation of squash reuse.
MICRO 2000: 223-234 |
| 54 | EE | Andreas Moshovos,
Gurindar S. Sohi:
Memory Dependence Prediction in Multimedia Applications.
J. Instruction-Level Parallelism 2: (2000) |
| 1999 |
|---|
| 53 | EE | Amir Roth,
Gurindar S. Sohi:
Effective Jump-Pointer Prefetching for Linked Data Structures.
ISCA 1999: 111-121 |
| 52 | EE | Amir Roth,
Andreas Moshovos,
Gurindar S. Sohi:
Improving virtual function call target prediction via dependence-based pre-computation.
International Conference on Supercomputing 1999: 356-364 |
| 51 | EE | Andreas Moshovos,
Gurindar S. Sohi:
Read-After-Read Memory Dependence Prediction.
MICRO 1999: 177-185 |
| 50 | EE | Craig B. Zilles,
Joel S. Emer,
Gurindar S. Sohi:
The Use of Multithreading for Exception Handling.
MICRO 1999: 219-229 |
| 49 | | Andreas Moshovos,
Gurindar S. Sohi:
Speculative Memory Cloaking and Bypassing.
International Journal of Parallel Programming 27(6): 427-456 (1999) |
| 48 | | T. N. Vijaykumar,
Gurindar S. Sohi:
Task Selection for the Multiscalar Architecture.
J. Parallel Distrib. Comput. 58(2): 132-158 (1999) |
| 1998 |
|---|
| 47 | EE | Gurindar S. Sohi:
Retrospective: Multiscalar Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 111-114 |
| 46 | EE | Gurindar S. Sohi,
Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 329-336 |
| 45 | EE | Gurindar S. Sohi:
Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 51-53 |
| 44 | EE | Gurindar S. Sohi,
Scott E. Breach,
T. N. Vijaykumar:
Multiscalar Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 521-532 |
| 43 | EE | Amir Roth,
Andreas Moshovos,
Gurindar S. Sohi:
Dependance Based Prefetching for Linked Data Structures.
ASPLOS 1998: 115-126 |
| 42 | EE | Avinash Sodani,
Gurindar S. Sohi:
An Empirical Analysis of Instruction Repetition.
ASPLOS 1998: 35-45 |
| 41 | EE | Sridhar Gopal,
T. N. Vijaykumar,
James E. Smith,
Gurindar S. Sohi:
Speculative Versioning Cache.
HPCA 1998: 195-205 |
| 40 | EE | Avinash Sodani,
Gurindar S. Sohi:
Understanding the Differences Between Value Prediction and Instruction Reuse.
MICRO 1998: 205-215 |
| 39 | EE | T. N. Vijaykumar,
Gurindar S. Sohi:
Task Selection for a Multiscalar Processor.
MICRO 1998: 81-92 |
| 1997 |
|---|
| 38 | EE | Andreas Moshovos,
Scott E. Breach,
T. N. Vijaykumar,
Gurindar S. Sohi:
Dynamic Speculation and Synchronization of Data Dependences.
ISCA 1997: 181-193 |
| 37 | EE | Avinash Sodani,
Gurindar S. Sohi:
Dynamic Instruction Reuse.
ISCA 1997: 194-205 |
| 36 | EE | Andreas Moshovos,
Gurindar S. Sohi:
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.
MICRO 1997: 235-245 |
| 35 | | Doug Burger,
James R. Goodman,
Gurindar S. Sohi:
Memory Systems.
The Computer Science and Engineering Handbook 1997: 447-461 |
| 1996 |
|---|
| 34 | EE | Todd M. Austin,
Gurindar S. Sohi:
High-Bandwidth Address Translation for Multiple-Issue Processors.
ISCA 1996: 158-167 |
| 33 | | Manoj Franklin,
Gurindar S. Sohi:
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References.
IEEE Trans. Computers 45(5): 552-571 (1996) |
| 1995 |
|---|
| 32 | EE | Todd M. Austin,
Dionisios N. Pnevmatikatos,
Gurindar S. Sohi:
Streamlining Data Cache Access with Fast Address Calculation.
ISCA 1995: 369-380 |
| 31 | EE | Gurindar S. Sohi,
Scott E. Breach,
T. N. Vijaykumar:
Multiscalar Processors.
ISCA 1995: 414-425 |
| 30 | EE | Todd M. Austin,
Gurindar S. Sohi:
Zero-cycle loads: microarchitecture support for reducing load latency.
MICRO 1995: 82-92 |
| 1994 |
|---|
| 29 | | Dionisios N. Pnevmatikatos,
Gurindar S. Sohi:
Guarded Executing and Branch Prediction in Dynamic ILP Processors.
ISCA 1994: 120-129 |
| 28 | EE | Scott E. Breach,
T. N. Vijaykumar,
Gurindar S. Sohi:
The anatomy of the register file in a multiscalar processor.
MICRO 1994: 181-190 |
| 27 | | Todd M. Austin,
Scott E. Breach,
Gurindar S. Sohi:
Efficient Detection of All Pointer and Array Access Errors.
PLDI 1994: 290-301 |
| 26 | EE | Alvin R. Lebeck,
Gurindar S. Sohi:
Request Combining in Multiprocessors with Arbitrary Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst. 5(11): 1140-1155 (1994) |
| 1993 |
|---|
| 25 | EE | Dionisios N. Pnevmatikatos,
Manoj Franklin,
Gurindar S. Sohi:
Control flow prediction for dynamic ILP processors.
MICRO 1993: 153-163 |
| 24 | | Gurindar S. Sohi:
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study.
IEEE Trans. Computers 42(1): 34-44 (1993) |
| 1992 |
|---|
| 23 | | Todd M. Austin,
Gurindar S. Sohi:
Dynamic Dependency Analysis of Ordinary Programs.
ISCA 1992: 342-351 |
| 22 | | Manoj Franklin,
Gurindar S. Sohi:
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism.
ISCA 1992: 58-67 |
| 21 | EE | Manoj Franklin,
Gurindar S. Sohi:
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors.
MICRO 1992: 236-245 |
| 20 | | MenChow Chiang,
Gurindar S. Sohi:
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment.
IEEE Trans. Computers 41(3): 297-317 (1992) |
| 1991 |
|---|
| 19 | | Gurindar S. Sohi,
Manoj Franklin:
High-Bandwidth Data Memory Systems for Superscalar Processors.
ASPLOS 1991: 53-62 |
| 18 | EE | Sriram Vajapeyam,
Gurindar S. Sohi,
Wei-Chung Hsu:
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks.
ISCA 1991: 170-179 |
| 17 | | MenChow Chiang,
Gurindar S. Sohi:
Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors.
SIGMETRICS 1991: 90-100 |
| 1990 |
|---|
| 16 | | Shreekant S. Thakkar,
Michel Dubois,
Anthony T. Laundrie,
Gurindar S. Sohi,
David V. James,
Stein Gjessing,
Manu Thapar,
Bruce Delagi,
Michael J. Carlton,
Alvin M. Despain:
Scalable Shared-Memory Multiprocessor Architectures.
IEEE Computer 23(6): 71-83 (1990) |
| 15 | | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers 39(1): 63-71 (1990) |
| 14 | | Gurindar S. Sohi:
Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers.
IEEE Trans. Computers 39(3): 349-359 (1990) |
| 13 | EE | Steven L. Scott,
Gurindar S. Sohi:
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control.
IEEE Trans. Parallel Distrib. Syst. 1(4): 385-398 (1990) |
| 1989 |
|---|
| 12 | | Gurindar S. Sohi,
Sriram Vajapeyam:
Tradeoffs in Instruction Format Design for Horizontal Architectures.
ASPLOS 1989: 15-25 |
| 11 | EE | Gurindar S. Sohi,
James E. Smith,
James R. Goodman:
Restricted Fetch&Phi operations for parallel processing.
ICS 1989: 410-416 |
| 10 | EE | Steven L. Scott,
Gurindar S. Sohi:
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks.
ISCA 1989: 167-176 |
| 9 | | V. S. Madan,
C.-J. Peng,
Gurindar S. Sohi:
On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns.
NACLP 1989: 888-906 |
| 8 | | Gurindar S. Sohi:
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.
IEEE Trans. Computers 38(4): 484-492 (1989) |
| 7 | | Mary K. Vernon,
Rajeev Jog,
Gurindar S. Sohi:
Performance Analysis of Hierarchical Cache-Consistent Multiprocessors.
Perform. Eval. 9(4): 287-302 (1989) |
| 1988 |
|---|
| 6 | | Andrew R. Pleszkun,
Gurindar S. Sohi:
The Performance Potential of Multiple Functional Unit Processors.
ISCA 1988: 37-44 |
| 5 | EE | Andrew R. Pleszkun,
Gurindar S. Sohi:
Multiple instruction issue and single-chip processors.
MICRO 1988: 64-66 |
| 1987 |
|---|
| 4 | EE | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
ISCA 1987: 224-231 |
| 3 | | Gurindar S. Sohi,
Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.
ISCA 1987: 27-34 |
| 1986 |
|---|
| 2 | | Andrew R. Pleszkun,
Gurindar S. Sohi,
Bassam Z. Kahhaleh,
Edward S. Davidson:
Features of the Structured Memory Access (SMA) Architecture.
COMPCON 1986: 259-265 |
| 1985 |
|---|
| 1 | | Gurindar S. Sohi,
Edward S. Davidson,
Janak H. Patel:
An Efficient LISP-Execution Architecture with a New Representation for List Structures.
ISCA 1985: 91-98 |
