| 1998 |
|---|
| 8 | EE | Byunggyu Kwak,
Eun Sei Park:
An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits.
DAC 1998: 690-693 |
| 1995 |
|---|
| 7 | | Sung Tae Jung,
Eun Sei Park,
Jung Sik Kim,
Chu Shik Jhon:
Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs.
ISCAS 1995: 1211-1214 |
| 1993 |
|---|
| 6 | | Eun Sei Park,
M. Ray Mercer:
Switch-Level ATPG Using Constraint-Guided Line Justification.
ITC 1993: 616-625 |
| 1992 |
|---|
| 5 | | Eun Sei Park,
M. Ray Mercer,
Thomas W. Williams:
The Total Delay Fault Model and Statistical Delay Fault Coverage.
IEEE Trans. Computers 41(6): 688-698 (1992) |
| 4 | EE | Eun Sei Park,
M. Ray Mercer:
An efficient delay test generation system for combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 926-938 (1992) |
| 1991 |
|---|
| 3 | | Eun Sei Park,
Bill Underwood,
Thomas W. Williams,
M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs.
ITC 1991: 897-905 |
| 1990 |
|---|
| 2 | EE | Eun Sei Park,
M. Ray Mercer:
An Efficient Delay Test Generation System for Combinational Logic Circuits.
DAC 1990: 522-528 |
| 1988 |
|---|
| 1 | | Eun Sei Park,
Thomas W. Williams,
M. Ray Mercer:
Statistical Delay Fault Coverage and Defect Level for Delay Faults.
ITC 1988: 492-499 |
