| 2003 |
|---|
| 11 | EE | Bruce D. Cory,
Rohit Kapur,
Bill Underwood:
Speed Binning with Path Delay Test in 150-nm Technology.
IEEE Design & Test of Computers 20(5): 41-45 (2003) |
| 1994 |
|---|
| 10 | | Sungho Kang,
Wai-On Law,
Bill Underwood:
Path-Delay Fault Simulation for a Standard Scan Design Methodology.
ICCD 1994: 359-362 |
| 9 | | Bill Underwood,
Wai-On Law,
Sungho Kang,
Haluk Konuk:
Fastpath: A Path-Delay Test Generator for Standard Scan Designs.
ITC 1994: 154-163 |
| 1991 |
|---|
| 8 | EE | Thomas W. Williams,
Bill Underwood,
M. Ray Mercer:
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing.
DAC 1991: 87-92 |
| 7 | | Eun Sei Park,
Bill Underwood,
Thomas W. Williams,
M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs.
ITC 1991: 897-905 |
| 1989 |
|---|
| 6 | | Bill Underwood,
Jack Ferguson:
The Parallel-Test-Detect Fault Simulation Algorithm.
ITC 1989: 712-717 |
| 1988 |
|---|
| 5 | | Steven P. Smith,
Bill Underwood,
Joe Newman:
An Analysis of Parallel Logic Simulation on Several Architectures.
ICPP (1) 1988: 65-68 |
| 4 | | Steven P. Smith,
Bill Underwood,
M. Ray Mercer:
D^3FS: A Demand Driven Deductive Fault Simulator.
ITC 1988: 582-592 |
| 1986 |
|---|
| 3 | | Rhonda Kay Gaede,
M. Ray Mercer,
Bill Underwood:
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm.
ITC 1986: 498-505 |
| 1985 |
|---|
| 2 | | John Salick,
Bill Underwood,
M. Ray Mercer:
Built-In Self Test Input Generator for Programmable Logic Arrays.
ITC 1985: 115-125 |
| 1984 |
|---|
| 1 | | Bill Underwood,
M. Ray Mercer:
Correlating Testability with Fault Detection.
ITC 1984: 697-704 |
