2005 |
21 | | Paolo Faverio,
Donatella Sciuto,
Giacomo Buonanno:
Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs.
ICEIS (1) 2005: 285-292 |
2000 |
20 | | Giacomo Buonanno,
Stefano Gramignoli,
Aurelio Ravarini,
Marco Tagliavini,
Donatella Sciuto:
ICT diffusion and strategic role within Italian SMEs.
IRMA Conference 2000: 373-378 |
1998 |
19 | EE | Marco Broglia,
Giacomo Buonanno,
Mariagiovanna Sami,
M. Selvini:
Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis.
DFT 1998: 312-317 |
1997 |
18 | EE | Cristiana Bolchini,
Giacomo Buonanno,
M. Cozzini,
Donatella Sciuto,
Renato Stefanelli:
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks.
DFT 1997: 204-211 |
17 | EE | Giacomo Buonanno,
Fabrizio Ferrandi,
L. Ferrandi,
Franco Fummi,
Donatella Sciuto:
How an "Evolving" Fault Model Improves the Behavioral Test Generation.
Great Lakes Symposium on VLSI 1997: 124- |
16 | | M. Bacis,
Giacomo Buonanno,
Fabrizio Ferrandi,
Franco Fummi,
Luca Gerli,
Donatella Sciuto:
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.
ICCD 1997: 654-658 |
15 | EE | Giacomo Buonanno,
M. Pugassi,
Mariagiovanna Sami:
A high-level synthesis approach to design of fault-tolerant systems.
VTS 1997: 356-363 |
1995 |
14 | | Giacomo Buonanno,
Fabio Salice,
Donatella Sciuto:
Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic.
ISCAS 1995: 1924-1927 |
13 | | Giacomo Buonanno,
Fabrizio Ferrandi,
Donatella Sciuto:
Data Path Testability Analysis Based on BDDs.
ISCAS 1995: 2012-2014 |
12 | EE | Cristiana Bolchini,
Giacomo Buonanno,
Donatella Sciuto,
Renato Stefanelli:
A new switching-level approach to multiple-output functions synthesis.
VLSI Design 1995: 125-129 |
11 | EE | Giacomo Buonanno,
Franco Fummi,
Donatella Sciuto:
TIES: A testability increase expert system for VLSI design.
J. Electronic Testing 6(2): 203-217 (1995) |
1994 |
10 | | Cristiana Bolchini,
Giacomo Buonanno,
Donatella Sciuto,
Renato Stefanelli:
A CMOS Fault Tolerant Architecture for Swith-Level Faults.
DFT 1994: 10-18 |
9 | | Cristiana Bolchini,
Giacomo Buonanno,
Donatella Sciuto,
Renato Stefanelli:
CMOS Reliability Improvements Through a New Fault Tolerant Technique.
ISCAS 1994: 83-86 |
8 | | Giacomo Buonanno,
Donatella Sciuto,
Renato Stefanelli:
Innovative Structures for CMOS Combinational Gates Synthesis.
IEEE Trans. Computers 43(4): 385-399 (1994) |
7 | EE | Massimo Bombana,
Giacomo Buonanno,
Patrizia Cavalloro,
Fabrizio Ferrandi,
Donatella Sciuto,
Giuseppe Zaza:
ALADIN: a multilevel testability analyzer for VLSI system design.
IEEE Trans. VLSI Syst. 2(2): 157-171 (1994) |
1993 |
6 | | Giacomo Buonanno,
Franco Fummi,
Donatella Sciuto:
Fault Detection in Sequential Circuits through Functional Testing.
DFT 1993: 191-198 |
5 | | Massimo Bombana,
Giacomo Buonanno,
Patrizia Cavalloro,
Fabrizio Ferrandi,
Donatella Sciuto,
Giuseppe Zaza:
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.
DFT 1993: 223-230 |
4 | | Giacomo Buonanno,
Franco Fummi,
Donatella Sciuto:
Functional Fault Models and Gate Level Coverage for Sequential Architectures.
ICCD 1993: 572-575 |
3 | | Giacomo Buonanno,
Franco Fummi,
Donatella Sciuto:
Functional Testing and Constrained Synthesis of Sequential Architectures.
ISCAS 1993: 1523-1526 |
2 | | Massimo Bombana,
Giacomo Buonanno,
Patrizia Cavalloro,
Fabrizio Ferrandi,
Donatella Sciuto,
Giuseppe Zaza:
An Expert Solution to Functional Testability Analysis of VLSI Circuits.
SEKE 1993: 263-265 |
1 | | Giacomo Buonanno,
Donatella Sciuto,
Renato Stefanelli:
New CMOS Structures for the Synthesis of Dominant Functions.
VLSI Design 1993: 367-370 |