S. Periyalwar

1993
2		William Robertson, S. Periyalwar, William J. Phillips: RTL Synthesis for Systolic Arrays. ISCAS 1993: 1670-1673
1992
1		A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson: Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays. Synthesis for Control Dominated Circuits 1992: 385-398

Coauthor Index

1	A. G. Jost	[1]
2	William J. Phillips	[2]
3	William Robertson	[1] [2]
4	L. F. Wang	[1]