1996 |
13 | EE | Razak Hossain,
Menghui Zheng,
Alexander Albicki:
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 361-368 (1996) |
1995 |
12 | EE | Yu Fang,
Alexander Albicki:
Efficient testability enhancement for combinational circuit.
ICCD 1995: 168-179 |
11 | EE | Menghui Zheng,
Alexander Albicki:
Low power and high speed multiplication design through mixed number representations.
ICCD 1995: 566-576 |
1994 |
10 | | Razak Hossain,
Menghui Zheng,
Alexander Albicki:
Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering.
ICCD 1994: 614-617 |
9 | EE | Razak Hossain,
Leszek D. Wronski,
Alexander Albicki:
Low power design using double edge triggered flip-flops.
IEEE Trans. VLSI Syst. 2(2): 261-265 (1994) |
1993 |
8 | | Xiaodong Xie,
Alexander Albicki:
Bit-Splitting for Testability Enhancement in Scan-Based Design.
ICCD 1993: 155-158 |
7 | | Razak Hossain,
Leszek D. Wronski,
Alexander Albicki:
Double Edge Triggered Devices: Speed and Power Considerations.
ISCAS 1993: 1491-1494 |
1992 |
6 | | Xiaodong Xie,
Alexander Albicki,
Andrzej Krasniewski:
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion.
ICCD 1992: 482-485 |
1991 |
5 | | Andrzej Krasniewski,
Alexander Albicki:
Random Testability of Redundant Circuits.
ICCD 1991: 424-427 |
1989 |
4 | | Robert F. Molyneaux,
Alexander Albicki:
Comments on "Ternary Scan Design for VLSI Testability".
IEEE Trans. Computers 38(2): 256-263 (1989) |
1985 |
3 | EE | Andrzej Krasniewski,
Alexander Albicki:
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications.
DAC 1985: 808-811 |
2 | | Andrzej Krasniewski,
Alexander Albicki:
Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules.
ITC 1985: 362-371 |
1 | | Carl Staelin,
Alexander Albicki:
Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control Units.
ITC 1985: 733-736 |